* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:23 ` [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations Hong Xu
@ 2011-08-19 9:37 ` Aneesh V
2011-08-19 9:46 ` Marek Vasut
2011-08-19 9:41 ` Marek Vasut
` (3 subsequent siblings)
4 siblings, 1 reply; 22+ messages in thread
From: Aneesh V @ 2011-08-19 9:37 UTC (permalink / raw)
To: u-boot
Hi Hong,
On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
How about converting as much as possible of these to armv5/armv6 generic
code as I mentioned in this thread:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=105526
On a quick look everything below except the "flush_dcache_all()" seems
to be armv5 generic.
best regards,
Aneesh
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Since V1
> Modified copyright line
> Fix for compiling warnings
> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> When unaligned buffer detected, emit ERROR instead of WARNING
>
> Do not make a common v5,v6 cache file. It seems arm946 is lack of
> Test-and-Clean DCache operation. And maybe more differents...
>
> arch/arm/cpu/arm926ejs/Makefile | 2 +-
> arch/arm/cpu/arm926ejs/cache.c | 135 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 136 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
> index 930e0d1..5b5f330 100644
> --- a/arch/arm/cpu/arm926ejs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/Makefile
> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
> LIB = $(obj)lib$(CPU).o
>
> START = start.o
> -COBJS = cpu.o
> +COBJS = cpu.o cache.o
>
> SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
> new file mode 100644
> index 0000000..756c9b1
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -0,0 +1,135 @@
> +/*
> + * (C) Copyright 2011 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#define FLUSH_CACHE_OP 0
> +#define INVALIDATE_CACHE_OP 1
> +
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +/*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
> + * only b'10, aka. 32 bytes cache line len is valid
> + */
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +#endif
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +/*
> + * Flush or Invalidate DCache respectively
> + */
> +static void cache_range_op(unsigned long start, unsigned long stop, int op)
> +{
> + unsigned long mva;
> +
> + if (op > INVALIDATE_CACHE_OP) {
> + printf("ERROR: %s - Invalid cache operation, op: %d!\n",
> + __func__, op);
> + return;
> + }
> +
> + mva = start;
> + if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, start,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round up starting address */
> + mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
> + }
> + if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, stop,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round down ending address */
> + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> + }
> +
> + while (mva < stop) {
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
> + else
> + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
> +
> + mva += CONFIG_SYS_CACHELINE_SIZE;
> + }
> +
> + /* Drain WB if necessary */
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> +}
> +
> +/*
> + * The buffer range to be flushed is [start, stop)
> + */
> +void flush_dcache_range(unsigned long start, unsigned long stop)
> +{
> + cache_range_op(start, stop, FLUSH_CACHE_OP);
> +}
> +
> +void flush_dcache_all(void)
> +{
> + /*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
> + * Clean & Invalidate the entire DCache
> + */
> + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
> + /* Drain WB */
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> +}
> +
> +void flush_cache(unsigned long start, unsigned long size)
> +{
> + flush_dcache_range(start, start + size);
> +}
> +
> +/*
> + * The buffer range to be invalidated is [start, stop)
> + */
> +void invalidate_dcache_range(unsigned long start, unsigned long stop)
> +{
> + cache_range_op(start, stop, INVALIDATE_CACHE_OP);
> +}
> +
> +void invalidate_dcache_all(void)
> +{
> + asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
> +}
> +
> +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +
> +void flush_cache(unsigned long start, unsigned long size) {}
> +void flush_dcache_all(void) {}
> +void flush_dcache_range(unsigned long start, unsigned long stop) {}
> +void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
> +void invalidate_dcache_all(void) {}
> +#endif
> +
> +#ifndef CONFIG_SYS_ICACHE_OFF
> +void invalidate_icache_all(void)
> +{
> + asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
> +}
> +
> +#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
> +
> +void invalidate_icache_all(void) {}
> +#endif
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:37 ` Aneesh V
@ 2011-08-19 9:46 ` Marek Vasut
2011-08-19 10:43 ` Aneesh V
0 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2011-08-19 9:46 UTC (permalink / raw)
To: u-boot
On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
> Hi Hong,
>
> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> > Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> > into this file.
>
> How about converting as much as possible of these to armv5/armv6 generic
> code as I mentioned in this thread:
>
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=105526
>
> On a quick look everything below except the "flush_dcache_all()" seems
> to be armv5 generic.
I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are
you dead sure it won't break any v5 CPU we support?
Cheers
>
> best regards,
> Aneesh
>
> > Signed-off-by: Hong Xu <hong.xu@atmel.com>
> > Tested-by: Elen Song <elen.song@atmel.com>
> > CC: Albert Aribaud <albert.u.boot@aribaud.net>
> > ---
> > Since V1
> >
> > Modified copyright line
> > Fix for compiling warnings
> > Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> > When unaligned buffer detected, emit ERROR instead of WARNING
> >
> > Do not make a common v5,v6 cache file. It seems arm946 is lack of
> > Test-and-Clean DCache operation. And maybe more differents...
> >
> > arch/arm/cpu/arm926ejs/Makefile | 2 +-
> > arch/arm/cpu/arm926ejs/cache.c | 135
> > +++++++++++++++++++++++++++++++++++++++ 2 files changed, 136
> > insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/cpu/arm926ejs/cache.c
> >
> > diff --git a/arch/arm/cpu/arm926ejs/Makefile
> > b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644
> > --- a/arch/arm/cpu/arm926ejs/Makefile
> > +++ b/arch/arm/cpu/arm926ejs/Makefile
> > @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
> >
> > LIB = $(obj)lib$(CPU).o
> >
> > START = start.o
> >
> > -COBJS = cpu.o
> > +COBJS = cpu.o cache.o
> >
> > SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> >
> > diff --git a/arch/arm/cpu/arm926ejs/cache.c
> > b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644
> > index 0000000..756c9b1
> > --- /dev/null
> > +++ b/arch/arm/cpu/arm926ejs/cache.c
> > @@ -0,0 +1,135 @@
> > +/*
> > + * (C) Copyright 2011 Atmel Corporation
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +
> > +#define FLUSH_CACHE_OP 0
> > +#define INVALIDATE_CACHE_OP 1
> > +
> > +#ifndef CONFIG_SYS_CACHELINE_SIZE
> > +/*
> > + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
> > + * only b'10, aka. 32 bytes cache line len is valid
> > + */
> > +#define CONFIG_SYS_CACHELINE_SIZE 32
> > +#endif
> > +
> > +#ifndef CONFIG_SYS_DCACHE_OFF
> > +/*
> > + * Flush or Invalidate DCache respectively
> > + */
> > +static void cache_range_op(unsigned long start, unsigned long stop, int
> > op) +{
> > + unsigned long mva;
> > +
> > + if (op > INVALIDATE_CACHE_OP) {
> > + printf("ERROR: %s - Invalid cache operation, op: %d!\n",
> > + __func__, op);
> > + return;
> > + }
> > +
> > + mva = start;
> > + if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> > + printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
> > + "to cache line size(%d bytes)\n", __func__, op, start,
> > + CONFIG_SYS_CACHELINE_SIZE);
> > + /* Round up starting address */
> > + mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
> > + }
> > + if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> > + printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
> > + "to cache line size(%d bytes)\n", __func__, op, stop,
> > + CONFIG_SYS_CACHELINE_SIZE);
> > + /* Round down ending address */
> > + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> > + }
> > +
> > + while (mva < stop) {
> > + if (op == FLUSH_CACHE_OP)
> > + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
> > + else
> > + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
> > +
> > + mva += CONFIG_SYS_CACHELINE_SIZE;
> > + }
> > +
> > + /* Drain WB if necessary */
> > + if (op == FLUSH_CACHE_OP)
> > + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> > +}
> > +
> > +/*
> > + * The buffer range to be flushed is [start, stop)
> > + */
> > +void flush_dcache_range(unsigned long start, unsigned long stop)
> > +{
> > + cache_range_op(start, stop, FLUSH_CACHE_OP);
> > +}
> > +
> > +void flush_dcache_all(void)
> > +{
> > + /*
> > + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
> > + * Clean & Invalidate the entire DCache
> > + */
> > + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
> > + /* Drain WB */
> > + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> > +}
> > +
> > +void flush_cache(unsigned long start, unsigned long size)
> > +{
> > + flush_dcache_range(start, start + size);
> > +}
> > +
> > +/*
> > + * The buffer range to be invalidated is [start, stop)
> > + */
> > +void invalidate_dcache_range(unsigned long start, unsigned long stop)
> > +{
> > + cache_range_op(start, stop, INVALIDATE_CACHE_OP);
> > +}
> > +
> > +void invalidate_dcache_all(void)
> > +{
> > + asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
> > +}
> > +
> > +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
> > +
> > +void flush_cache(unsigned long start, unsigned long size) {}
> > +void flush_dcache_all(void) {}
> > +void flush_dcache_range(unsigned long start, unsigned long stop) {}
> > +void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
> > +void invalidate_dcache_all(void) {}
> > +#endif
> > +
> > +#ifndef CONFIG_SYS_ICACHE_OFF
> > +void invalidate_icache_all(void)
> > +{
> > + asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
> > +}
> > +
> > +#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
> > +
> > +void invalidate_icache_all(void) {}
> > +#endif
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:46 ` Marek Vasut
@ 2011-08-19 10:43 ` Aneesh V
2011-08-19 12:55 ` Marek Vasut
0 siblings, 1 reply; 22+ messages in thread
From: Aneesh V @ 2011-08-19 10:43 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Friday 19 August 2011 03:16 PM, Marek Vasut wrote:
> On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
>> Hi Hong,
>>
>> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
>>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>>> into this file.
>>
>> How about converting as much as possible of these to armv5/armv6 generic
>> code as I mentioned in this thread:
>>
>> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=105526
>>
>> On a quick look everything below except the "flush_dcache_all()" seems
>> to be armv5 generic.
>
> I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are
> you dead sure it won't break any v5 CPU we support?
>
What Hong has used is operations mentioned in the ARMv5 architecture
and these are not marked as IMPLEMENTATION DEFINED. So, compliant
implementations should implement those CP15 operations. They may
enhance the operations by adding their own like ARM926EJS seems to be
doing with 'flush d-cache all'.
However, I think that's immaterial. Hong can provide this as a library
and define a CONFIG_* flag to enable it. Let the platform maintainers
decide whether to use it or not. IMHO, it will definitely be an
improvement over what we have today.
best regards,
Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 10:43 ` Aneesh V
@ 2011-08-19 12:55 ` Marek Vasut
2011-08-19 14:16 ` Aneesh V
0 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2011-08-19 12:55 UTC (permalink / raw)
To: u-boot
On Friday, August 19, 2011 12:43:30 PM Aneesh V wrote:
> Hi Marek,
>
> On Friday 19 August 2011 03:16 PM, Marek Vasut wrote:
> > On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
> >> Hi Hong,
> >>
> >> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> >>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> >>> into this file.
> >>
> >> How about converting as much as possible of these to armv5/armv6 generic
> >> code as I mentioned in this thread:
> >>
> >> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=1055
> >> 26
> >>
> >> On a quick look everything below except the "flush_dcache_all()" seems
> >> to be armv5 generic.
> >
> > I'd be _VERY_ careful here. And this "seems" doesn't sound very
> > convincing. Are you dead sure it won't break any v5 CPU we support?
>
> What Hong has used is operations mentioned in the ARMv5 architecture
> and these are not marked as IMPLEMENTATION DEFINED. So, compliant
> implementations should implement those CP15 operations. They may
> enhance the operations by adding their own like ARM926EJS seems to be
> doing with 'flush d-cache all'.
>
> However, I think that's immaterial. Hong can provide this as a library
> and define a CONFIG_* flag to enable it. Let the platform maintainers
> decide whether to use it or not. IMHO, it will definitely be an
> improvement over what we have today.
Hi,
It certainly will, but I'm quite relucant to that as it'll also -- since
CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default -- break
some things. Even though what I said is not exactly an argument for what you
said.
If you're firm all ARMv5 implement it this way, I'm all for it being done the way
you suggest it!
Thanks
>
> best regards,
> Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 12:55 ` Marek Vasut
@ 2011-08-19 14:16 ` Aneesh V
2011-08-28 19:16 ` Marek Vasut
0 siblings, 1 reply; 22+ messages in thread
From: Aneesh V @ 2011-08-19 14:16 UTC (permalink / raw)
To: u-boot
On Friday 19 August 2011 06:25 PM, Marek Vasut wrote:
> On Friday, August 19, 2011 12:43:30 PM Aneesh V wrote:
>> Hi Marek,
>>
>> On Friday 19 August 2011 03:16 PM, Marek Vasut wrote:
>>> On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
>>>> Hi Hong,
>>>>
>>>> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
>>>>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>>>>> into this file.
>>>>
>>>> How about converting as much as possible of these to armv5/armv6 generic
>>>> code as I mentioned in this thread:
>>>>
>>>> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=1055
>>>> 26
>>>>
>>>> On a quick look everything below except the "flush_dcache_all()" seems
>>>> to be armv5 generic.
>>>
>>> I'd be _VERY_ careful here. And this "seems" doesn't sound very
>>> convincing. Are you dead sure it won't break any v5 CPU we support?
>>
>> What Hong has used is operations mentioned in the ARMv5 architecture
>> and these are not marked as IMPLEMENTATION DEFINED. So, compliant
>> implementations should implement those CP15 operations. They may
>> enhance the operations by adding their own like ARM926EJS seems to be
>> doing with 'flush d-cache all'.
>>
>> However, I think that's immaterial. Hong can provide this as a library
>> and define a CONFIG_* flag to enable it. Let the platform maintainers
>> decide whether to use it or not. IMHO, it will definitely be an
>> improvement over what we have today.
>
> Hi,
>
> It certainly will, but I'm quite relucant to that as it'll also -- since
> CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default -- break
> some things. Even though what I said is not exactly an argument for what you
> said.
>
> If you're firm all ARMv5 implement it this way, I'm all for it being done the way
> you suggest it!
I can not vouch for all the CPUs. But I checked one more - ARM946ES.
This one is also implementing all the standard operations that Hong has
used('flush d-cache all' used by Hong is not a standard armv5
operation - that seems to be a 926ejs specific one).
best regards,
Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 14:16 ` Aneesh V
@ 2011-08-28 19:16 ` Marek Vasut
0 siblings, 0 replies; 22+ messages in thread
From: Marek Vasut @ 2011-08-28 19:16 UTC (permalink / raw)
To: u-boot
On Friday, August 19, 2011 04:16:44 PM Aneesh V wrote:
> On Friday 19 August 2011 06:25 PM, Marek Vasut wrote:
> > On Friday, August 19, 2011 12:43:30 PM Aneesh V wrote:
> >> Hi Marek,
> >>
> >> On Friday 19 August 2011 03:16 PM, Marek Vasut wrote:
> >>> On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
> >>>> Hi Hong,
> >>>>
> >>>> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> >>>>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache
> >>>>> operations into this file.
> >>>>
> >>>> How about converting as much as possible of these to armv5/armv6
> >>>> generic code as I mentioned in this thread:
> >>>>
> >>>> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=10
> >>>> 55 26
> >>>>
> >>>> On a quick look everything below except the "flush_dcache_all()" seems
> >>>> to be armv5 generic.
> >>>
> >>> I'd be _VERY_ careful here. And this "seems" doesn't sound very
> >>> convincing. Are you dead sure it won't break any v5 CPU we support?
> >>
> >> What Hong has used is operations mentioned in the ARMv5 architecture
> >> and these are not marked as IMPLEMENTATION DEFINED. So, compliant
> >> implementations should implement those CP15 operations. They may
> >> enhance the operations by adding their own like ARM926EJS seems to be
> >> doing with 'flush d-cache all'.
> >>
> >> However, I think that's immaterial. Hong can provide this as a library
> >> and define a CONFIG_* flag to enable it. Let the platform maintainers
> >> decide whether to use it or not. IMHO, it will definitely be an
> >> improvement over what we have today.
> >
> > Hi,
> >
> > It certainly will, but I'm quite relucant to that as it'll also -- since
> > CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default
> > -- break some things. Even though what I said is not exactly an argument
> > for what you said.
> >
> > If you're firm all ARMv5 implement it this way, I'm all for it being done
> > the way you suggest it!
>
> I can not vouch for all the CPUs. But I checked one more - ARM946ES.
> This one is also implementing all the standard operations that Hong has
> used('flush d-cache all' used by Hong is not a standard armv5
> operation - that seems to be a 926ejs specific one).
Dear Aneesh,
today I looked into Xscale cache ops. Xscale (ARMv5) seems to have the
invalidation operations implemented, but it is missing the flush operations.
MRC p15, 0, r15, c7, c14, 3
won't work. Or more like anything with c14 won't. The cache flushing is done
differently on Xscale, but that is probably only a matter of Xscale. I need to
investigate how to handle the Xscale flush ops, there is code for that in Linux.
Best regards
Marek Vasut
>
> best regards,
> Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:23 ` [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations Hong Xu
2011-08-19 9:37 ` Aneesh V
@ 2011-08-19 9:41 ` Marek Vasut
2011-08-19 10:17 ` Lei Wen
` (2 subsequent siblings)
4 siblings, 0 replies; 22+ messages in thread
From: Marek Vasut @ 2011-08-19 9:41 UTC (permalink / raw)
To: u-boot
On Friday, August 19, 2011 11:23:15 AM Hong Xu wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
You can add my:
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Cheers!
> ---
> Since V1
> Modified copyright line
> Fix for compiling warnings
> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> When unaligned buffer detected, emit ERROR instead of WARNING
>
> Do not make a common v5,v6 cache file. It seems arm946 is lack of
> Test-and-Clean DCache operation. And maybe more differents...
>
> arch/arm/cpu/arm926ejs/Makefile | 2 +-
> arch/arm/cpu/arm926ejs/cache.c | 135
> +++++++++++++++++++++++++++++++++++++++ 2 files changed, 136
> insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/Makefile
> b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644
> --- a/arch/arm/cpu/arm926ejs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/Makefile
> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
> LIB = $(obj)lib$(CPU).o
>
> START = start.o
> -COBJS = cpu.o
> +COBJS = cpu.o cache.o
>
> SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/arch/arm/cpu/arm926ejs/cache.c
> b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644
> index 0000000..756c9b1
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -0,0 +1,135 @@
> +/*
> + * (C) Copyright 2011 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#define FLUSH_CACHE_OP 0
> +#define INVALIDATE_CACHE_OP 1
> +
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +/*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
> + * only b'10, aka. 32 bytes cache line len is valid
> + */
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +#endif
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +/*
> + * Flush or Invalidate DCache respectively
> + */
> +static void cache_range_op(unsigned long start, unsigned long stop, int
> op) +{
> + unsigned long mva;
> +
> + if (op > INVALIDATE_CACHE_OP) {
> + printf("ERROR: %s - Invalid cache operation, op: %d!\n",
> + __func__, op);
> + return;
> + }
> +
> + mva = start;
> + if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, start,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round up starting address */
> + mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
> + }
> + if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, stop,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round down ending address */
> + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> + }
> +
> + while (mva < stop) {
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
> + else
> + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
> +
> + mva += CONFIG_SYS_CACHELINE_SIZE;
> + }
> +
> + /* Drain WB if necessary */
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> +}
> +
> +/*
> + * The buffer range to be flushed is [start, stop)
> + */
> +void flush_dcache_range(unsigned long start, unsigned long stop)
> +{
> + cache_range_op(start, stop, FLUSH_CACHE_OP);
> +}
> +
> +void flush_dcache_all(void)
> +{
> + /*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
> + * Clean & Invalidate the entire DCache
> + */
> + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
> + /* Drain WB */
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> +}
> +
> +void flush_cache(unsigned long start, unsigned long size)
> +{
> + flush_dcache_range(start, start + size);
> +}
> +
> +/*
> + * The buffer range to be invalidated is [start, stop)
> + */
> +void invalidate_dcache_range(unsigned long start, unsigned long stop)
> +{
> + cache_range_op(start, stop, INVALIDATE_CACHE_OP);
> +}
> +
> +void invalidate_dcache_all(void)
> +{
> + asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
> +}
> +
> +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +
> +void flush_cache(unsigned long start, unsigned long size) {}
> +void flush_dcache_all(void) {}
> +void flush_dcache_range(unsigned long start, unsigned long stop) {}
> +void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
> +void invalidate_dcache_all(void) {}
> +#endif
> +
> +#ifndef CONFIG_SYS_ICACHE_OFF
> +void invalidate_icache_all(void)
> +{
> + asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
> +}
> +
> +#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
> +
> +void invalidate_icache_all(void) {}
> +#endif
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:23 ` [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations Hong Xu
2011-08-19 9:37 ` Aneesh V
2011-08-19 9:41 ` Marek Vasut
@ 2011-08-19 10:17 ` Lei Wen
2011-08-19 10:30 ` Hong Xu
2011-08-19 10:31 ` Lei Wen
2011-08-19 14:20 ` Aneesh V
4 siblings, 1 reply; 22+ messages in thread
From: Lei Wen @ 2011-08-19 10:17 UTC (permalink / raw)
To: u-boot
Hi Hong,
On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu <hong.xu@atmel.com> wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Since V1
> ? ?Modified copyright line
> ? ?Fix for compiling warnings
> ? ?Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> ? ?When unaligned buffer detected, emit ERROR instead of WARNING
>
> ? ?Do not make a common v5,v6 cache file. It seems arm946 is lack of
> ? ?Test-and-Clean DCache operation. And maybe more differents...
>
> ?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +-
> ?arch/arm/cpu/arm926ejs/cache.c ?| ?135 +++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 136 insertions(+), 1 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>
This patch series don't works for me. My board is also arm926ejs
based, and its configure as dkb_config;
The error message as below:
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be30 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c030 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be28 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
cache line size(32 bytes)
Do you have any hint for this?
Best regards,
Lei
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 10:17 ` Lei Wen
@ 2011-08-19 10:30 ` Hong Xu
0 siblings, 0 replies; 22+ messages in thread
From: Hong Xu @ 2011-08-19 10:30 UTC (permalink / raw)
To: u-boot
Hi Wen,
On 08/19/2011 06:17 PM, Lei Wen wrote:
> Hi Hong,
>
> On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu<hong.xu@atmel.com> wrote:
>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>> into this file.
>>
>> Signed-off-by: Hong Xu<hong.xu@atmel.com>
>> Tested-by: Elen Song<elen.song@atmel.com>
>> CC: Albert Aribaud<albert.u.boot@aribaud.net>
>> ---
>> Since V1
>> Modified copyright line
>> Fix for compiling warnings
>> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
>> When unaligned buffer detected, emit ERROR instead of WARNING
>>
>> Do not make a common v5,v6 cache file. It seems arm946 is lack of
>> Test-and-Clean DCache operation. And maybe more differents...
>>
>> arch/arm/cpu/arm926ejs/Makefile | 2 +-
>> arch/arm/cpu/arm926ejs/cache.c | 135 +++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 136 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>>
>
> This patch series don't works for me. My board is also arm926ejs
> based, and its configure as dkb_config;
> The error message as below:
> ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
> cache line size(32 bytes)
> ERROR: cache_range_op op: 0 - start address 0x1fe7be30 not aligned to
> cache line size(32 bytes)
> ERROR: cache_range_op op: 0 - stop address 0x1fe7c030 not aligned to
> cache line size(32 bytes)
> ERROR: cache_range_op op: 0 - start address 0x1fe7be28 not aligned to
> cache line size(32 bytes)
> ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
> cache line size(32 bytes)
The APIs need the buffer address passed is cache-line size aligned. You
shall take the alignment into account in your driver code. Try to use
memalign() or something similar in your driver code?
BR,
Eric
> Do you have any hint for this?
>
> Best regards,
> Lei
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:23 ` [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations Hong Xu
` (2 preceding siblings ...)
2011-08-19 10:17 ` Lei Wen
@ 2011-08-19 10:31 ` Lei Wen
2011-08-22 2:03 ` Hong Xu
2011-08-19 14:20 ` Aneesh V
4 siblings, 1 reply; 22+ messages in thread
From: Lei Wen @ 2011-08-19 10:31 UTC (permalink / raw)
To: u-boot
Hi Hong,
On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu <hong.xu@atmel.com> wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Since V1
> ? ?Modified copyright line
> ? ?Fix for compiling warnings
> ? ?Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> ? ?When unaligned buffer detected, emit ERROR instead of WARNING
>
> ? ?Do not make a common v5,v6 cache file. It seems arm946 is lack of
> ? ?Test-and-Clean DCache operation. And maybe more differents...
>
> ?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +-
> ?arch/arm/cpu/arm926ejs/cache.c ?| ?135 +++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 136 insertions(+), 1 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
> index 930e0d1..5b5f330 100644
> --- a/arch/arm/cpu/arm926ejs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/Makefile
> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
> ?LIB ? ?= $(obj)lib$(CPU).o
>
> ?START ?= start.o
> -COBJS ?= cpu.o
> +COBJS ?= cpu.o cache.o
>
> ?SRCS ? := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> ?OBJS ? := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
> new file mode 100644
> index 0000000..756c9b1
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -0,0 +1,135 @@
> +/*
> + * (C) Copyright 2011 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#define FLUSH_CACHE_OP ? ? ? ? 0
> +#define INVALIDATE_CACHE_OP ? ?1
> +
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +/*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
> + * only b'10, aka. 32 bytes cache line len is valid
> + */
> +#define CONFIG_SYS_CACHELINE_SIZE 32
I think we shouldn't make such assumption here.
You could refer to Lukasz's patch over armv7:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772
And you also should export one method as: get_dcache_line_size(), so
that we could malloc cache aligned buffer in mmc.c.
Best regards,
Lei
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 10:31 ` Lei Wen
@ 2011-08-22 2:03 ` Hong Xu
0 siblings, 0 replies; 22+ messages in thread
From: Hong Xu @ 2011-08-22 2:03 UTC (permalink / raw)
To: u-boot
Hi Lei,
On 08/19/2011 06:31 PM, Lei Wen wrote:
> Hi Hong,
>
> On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu<hong.xu@atmel.com> wrote:
>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>> into this file.
>>
>> Signed-off-by: Hong Xu<hong.xu@atmel.com>
>> Tested-by: Elen Song<elen.song@atmel.com>
>> CC: Albert Aribaud<albert.u.boot@aribaud.net>
>> ---
>> Since V1
>> Modified copyright line
>> Fix for compiling warnings
>> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
>> When unaligned buffer detected, emit ERROR instead of WARNING
>>
>> Do not make a common v5,v6 cache file. It seems arm946 is lack of
>> Test-and-Clean DCache operation. And maybe more differents...
>>
>> arch/arm/cpu/arm926ejs/Makefile | 2 +-
>> arch/arm/cpu/arm926ejs/cache.c | 135 +++++++++++++++++++++++++++++++++++++++
[..]
>> +#include<common.h>
>> +
>> +#define FLUSH_CACHE_OP 0
>> +#define INVALIDATE_CACHE_OP 1
>> +
>> +#ifndef CONFIG_SYS_CACHELINE_SIZE
>> +/*
>> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
>> + * only b'10, aka. 32 bytes cache line len is valid
>> + */
>> +#define CONFIG_SYS_CACHELINE_SIZE 32
>
> I think we shouldn't make such assumption here.
> You could refer to Lukasz's patch over armv7:
> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772
> And you also should export one method as: get_dcache_line_size(), so
> that we could malloc cache aligned buffer in mmc.c.
There was a long loop about this, see
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105113/focus=105137
I agree we may need something like get_dcache_line_size(). This will
make driver sane if CONFIG_SYS_CACHELINE_SIZE is not defined.
BR,
Eric
> Best regards,
> Lei
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 9:23 ` [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations Hong Xu
` (3 preceding siblings ...)
2011-08-19 10:31 ` Lei Wen
@ 2011-08-19 14:20 ` Aneesh V
2011-08-22 2:14 ` Hong Xu
4 siblings, 1 reply; 22+ messages in thread
From: Aneesh V @ 2011-08-19 14:20 UTC (permalink / raw)
To: u-boot
Hi Hong,
On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Since V1
> Modified copyright line
> Fix for compiling warnings
> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> When unaligned buffer detected, emit ERROR instead of WARNING
>
> Do not make a common v5,v6 cache file. It seems arm946 is lack of
> Test-and-Clean DCache operation. And maybe more differents...
>
> arch/arm/cpu/arm926ejs/Makefile | 2 +-
> arch/arm/cpu/arm926ejs/cache.c | 135 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 136 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
> index 930e0d1..5b5f330 100644
> --- a/arch/arm/cpu/arm926ejs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/Makefile
> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
> LIB = $(obj)lib$(CPU).o
>
> START = start.o
> -COBJS = cpu.o
> +COBJS = cpu.o cache.o
>
> SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
> new file mode 100644
> index 0000000..756c9b1
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -0,0 +1,135 @@
> +/*
> + * (C) Copyright 2011 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#define FLUSH_CACHE_OP 0
> +#define INVALIDATE_CACHE_OP 1
> +
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +/*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
> + * only b'10, aka. 32 bytes cache line len is valid
> + */
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +#endif
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +/*
> + * Flush or Invalidate DCache respectively
> + */
> +static void cache_range_op(unsigned long start, unsigned long stop, int op)
> +{
> + unsigned long mva;
> +
> + if (op > INVALIDATE_CACHE_OP) {
> + printf("ERROR: %s - Invalid cache operation, op: %d!\n",
> + __func__, op);
> + return;
> + }
> +
> + mva = start;
> + if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, start,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round up starting address */
> + mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
> + }
> + if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
> + printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
> + "to cache line size(%d bytes)\n", __func__, op, stop,
> + CONFIG_SYS_CACHELINE_SIZE);
> + /* Round down ending address */
> + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> + }
> +
> + while (mva < stop) {
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
> + else
> + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
> +
> + mva += CONFIG_SYS_CACHELINE_SIZE;
> + }
> +
> + /* Drain WB if necessary */
> + if (op == FLUSH_CACHE_OP)
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
> +}
> +
> +/*
> + * The buffer range to be flushed is [start, stop)
> + */
> +void flush_dcache_range(unsigned long start, unsigned long stop)
> +{
> + cache_range_op(start, stop, FLUSH_CACHE_OP);
> +}
> +
> +void flush_dcache_all(void)
> +{
> + /*
> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
> + * Clean & Invalidate the entire DCache
> + */
> + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
> + /* Drain WB */
> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
While looking at the manuals for the armv5 compatibility I stumbled
upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all
implementation is correct? I suspect the above is flushing only one
line?
"The test, clean, and invalidate DCache instruction is the same as test
and clean DCache,
except that when the entire cache has been cleaned, it is invalidated.
This means that
you can use the following loop to clean and invalidate the entire
DCache:
tci_loop: MRC p15, 0, r15, c7, c14, 3
BNE tci_loop
"
best regards,
Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-19 14:20 ` Aneesh V
@ 2011-08-22 2:14 ` Hong Xu
2011-08-22 3:31 ` V, Aneesh
0 siblings, 1 reply; 22+ messages in thread
From: Hong Xu @ 2011-08-22 2:14 UTC (permalink / raw)
To: u-boot
Hi Aneesh,
On 08/19/2011 10:20 PM, Aneesh V wrote:
> Hi Hong,
>
> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>> into this file.
>>
>> Signed-off-by: Hong Xu<hong.xu@atmel.com>
>> Tested-by: Elen Song<elen.song@atmel.com>
>> CC: Albert Aribaud<albert.u.boot@aribaud.net>
>> ---
>> Since V1
>> Modified copyright line
>> Fix for compiling warnings
>> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
>> When unaligned buffer detected, emit ERROR instead of WARNING
>>
>> Do not make a common v5,v6 cache file. It seems arm946 is lack of
>> Test-and-Clean DCache operation. And maybe more differents...
>>
>> arch/arm/cpu/arm926ejs/Makefile | 2 +-
>> arch/arm/cpu/arm926ejs/cache.c | 135 +++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 136 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>>
[...]
>> +
>> +/*
>> + * The buffer range to be flushed is [start, stop)
>> + */
>> +void flush_dcache_range(unsigned long start, unsigned long stop)
>> +{
>> + cache_range_op(start, stop, FLUSH_CACHE_OP);
>> +}
>> +
>> +void flush_dcache_all(void)
>> +{
>> + /*
>> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
>> + * Clean& Invalidate the entire DCache
>> + */
>> + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
>> + /* Drain WB */
>> + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
>
> While looking at the manuals for the armv5 compatibility I stumbled
> upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all
> implementation is correct? I suspect the above is flushing only one
> line?
>
> "The test, clean, and invalidate DCache instruction is the same as test
> and clean DCache,
> except that when the entire cache has been cleaned, it is invalidated.
> This means that
> you can use the following loop to clean and invalidate the entire
> DCache:
>
> tci_loop: MRC p15, 0, r15, c7, c14, 3
> BNE tci_loop
> "
As stated in the manual, we can use a loop to clean and invalidate the
entire DCache.
The "asm" statement above is a loop, isn't it? ;-)
BR,
Eric
> best regards,
> Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
2011-08-22 2:14 ` Hong Xu
@ 2011-08-22 3:31 ` V, Aneesh
0 siblings, 0 replies; 22+ messages in thread
From: V, Aneesh @ 2011-08-22 3:31 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Mon, Aug 22, 2011 at 7:44 AM, Hong Xu <hong.xu@atmel.com> wrote:
> Hi Aneesh,
>
> On 08/19/2011 10:20 PM, Aneesh V wrote:
>>
>> Hi Hong,
>>
>> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
>>>
>>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>>> into this file.
>>>
>>> Signed-off-by: Hong Xu<hong.xu@atmel.com>
>>> Tested-by: Elen Song<elen.song@atmel.com>
>>> CC: Albert Aribaud<albert.u.boot@aribaud.net>
>>> ---
>>> Since V1
>>> ? ? Modified copyright line
>>> ? ? Fix for compiling warnings
>>> ? ? Changed the way to use CONFIG_SYS_CACHELINE_SIZE
>>> ? ? When unaligned buffer detected, emit ERROR instead of WARNING
>>>
>>> ? ? Do not make a common v5,v6 cache file. It seems arm946 is lack of
>>> ? ? Test-and-Clean DCache operation. And maybe more differents...
>>>
>>> ?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +-
>>> ?arch/arm/cpu/arm926ejs/cache.c ?| ?135
>>> +++++++++++++++++++++++++++++++++++++++
>>> ?2 files changed, 136 insertions(+), 1 deletions(-)
>>> ?create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>>>
>
> [...]
>
>>> +
>>> +/*
>>> + * The buffer range to be flushed is [start, stop)
>>> + */
>>> +void flush_dcache_range(unsigned long start, unsigned long stop)
>>> +{
>>> + ? ? ? cache_range_op(start, stop, FLUSH_CACHE_OP);
>>> +}
>>> +
>>> +void flush_dcache_all(void)
>>> +{
>>> + ? ? ? /*
>>> + ? ? ? ?* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
>>> + ? ? ? ?* Clean& ?Invalidate the entire DCache
>>> + ? ? ? ?*/
>>> + ? ? ? asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : :
>>> "memory");
>>> + ? ? ? /* Drain WB */
>>> + ? ? ? asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
>>
>> While looking at the manuals for the armv5 compatibility I stumbled
>> upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all
>> implementation is correct? I suspect the above is flushing only one
>> line?
>>
>> "The test, clean, and invalidate DCache instruction is the same as test
>> and clean DCache,
>> except that when the entire cache has been cleaned, it is invalidated.
>> This means that
>> you can use the following loop to clean and invalidate the entire
>> DCache:
>>
>> tci_loop: ? ? MRC p15, 0, r15, c7, c14, 3
>> ? ? ? ? ? ? ? BNE tci_loop
>> "
>
> As stated in the manual, we can use a loop to clean and invalidate the
> entire DCache.
>
> The "asm" statement above is a loop, isn't it? ;-)
Oops! I didn't notice that. Sorry for the noise. But, maybe, it could be made
two separate lines to make it more readable.
br,
Aneesh
^ permalink raw reply [flat|nested] 22+ messages in thread