From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Sun, 28 Aug 2011 21:16:25 +0200
Subject: [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
In-Reply-To: <4E4E704C.8030103@ti.com>
References: <1313745795-1326-1-git-send-email-hong.xu@atmel.com>
	<201108191455.52899.marek.vasut@gmail.com>
	<4E4E704C.8030103@ti.com>
Message-ID: <201108282116.26096.marek.vasut@gmail.com>
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On Friday, August 19, 2011 04:16:44 PM Aneesh V wrote:
> On Friday 19 August 2011 06:25 PM, Marek Vasut wrote:
> > On Friday, August 19, 2011 12:43:30 PM Aneesh V wrote:
> >> Hi Marek,
> >> 
> >> On Friday 19 August 2011 03:16 PM, Marek Vasut wrote:
> >>> On Friday, August 19, 2011 11:37:29 AM Aneesh V wrote:
> >>>> Hi Hong,
> >>>> 
> >>>> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
> >>>>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache
> >>>>> operations into this file.
> >>>> 
> >>>> How about converting as much as possible of these to armv5/armv6
> >>>> generic code as I mentioned in this thread:
> >>>> 
> >>>> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=10
> >>>> 55 26
> >>>> 
> >>>> On a quick look everything below except the "flush_dcache_all()" seems
> >>>> to be armv5 generic.
> >>> 
> >>> I'd be _VERY_ careful here. And this "seems" doesn't sound very
> >>> convincing. Are you dead sure it won't break any v5 CPU we support?
> >> 
> >> What Hong has used is operations mentioned in the ARMv5 architecture
> >> and these are not marked as IMPLEMENTATION DEFINED. So, compliant
> >> implementations should implement those CP15 operations. They may
> >> enhance the operations by adding their own like ARM926EJS seems to be
> >> doing with 'flush d-cache all'.
> >> 
> >> However, I think that's immaterial. Hong can provide this as a library
> >> and define a CONFIG_* flag to enable it. Let the platform maintainers
> >> decide whether to use it or not. IMHO, it will definitely be an
> >> improvement over what we have today.
> > 
> > Hi,
> > 
> > It certainly will, but I'm quite relucant to that as it'll also -- since
> > CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default
> > -- break some things. Even though what I said is not exactly an argument
> > for what you said.
> > 
> > If you're firm all ARMv5 implement it this way, I'm all for it being done
> > the way you suggest it!
> 
> I can not vouch for all the CPUs. But I checked one more - ARM946ES.
> This one is also implementing all the standard operations that Hong has
> used('flush d-cache all' used by Hong is not a standard armv5
> operation - that seems to be a 926ejs specific one).

Dear Aneesh,

today I looked into Xscale cache ops. Xscale (ARMv5) seems to have the 
invalidation operations implemented, but it is missing the flush operations.

MRC p15, 0, r15, c7, c14, 3

won't work. Or more like anything with c14 won't. The cache flushing is done 
differently on Xscale, but that is probably only a matter of Xscale. I need to 
investigate how to handle the Xscale flush ops, there is code for that in Linux.

Best regards
Marek Vasut

> 
> best regards,
> Aneesh