[U-Boot] [PATCH] dcache: Dcache line size aligned stack buffer allocation

[Mike Frysinger <vapier@gentoo.org>]

On Thursday, August 25, 2011 05:34:00 Wolfgang Denk wrote:
> CONFIG_SYS_CACHELINE_SIZE is a mandatory #define, and it's OK that a
> build breaks when it's missing.  On the other hand I don;t se why this
> macro needs top be removed when the data cache is off.

i guess a lot of arch people will need to post updates.  this seems to be 
available for all ppc and mips peeps, and one arm soc.  everyone else gets a 
fun build fail.

however, cacheline size is an aspect of the cpu core and doesnt really make 
sense as a board config.  even the ppc header hints at this:
/*
 * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
 */
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE   L1_CACHE_BYTES
#endif

so my proposal is to migrate away from CONFIG_SYS_CACHELINE_SIZE and to the 
API that Linux has adopted:
asm/cache.h: define L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN

then we build ALLOC_CACHE_ALIGN_BUFFER() on top of the ARCH_DMA_MINALIGN 
define (since that's the point of that define in the first place)
-mike
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