[U-Boot] [PATCH 2/4] MX5: Add AHB clock reporting and fix IPG clock reporting

[Marek Vasut <marek.vasut@gmail.com>]

On Thursday, September 22, 2011 05:05:43 AM Jason Hui wrote:
> Hi, Marek
> 
> On Thu, Sep 15, 2011 at 8:09 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> > Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> > ---
> >  arch/arm/cpu/armv7/mx5/clock.c |   36
> > +++++++++++++++++++++++++++--------- 1 files changed, 27 insertions(+),
> > 9 deletions(-)
> > 
> > diff --git a/arch/arm/cpu/armv7/mx5/clock.c
> > b/arch/arm/cpu/armv7/mx5/clock.c index 9f37f7f..a9fe81c 100644
> > --- a/arch/arm/cpu/armv7/mx5/clock.c
> > +++ b/arch/arm/cpu/armv7/mx5/clock.c
> > @@ -152,18 +152,35 @@ static u32 get_periph_clk(void)
> >  }
> > 
> >  /*
> > + * Get the rate of ahb clock.
> > + */
> > +static u32 get_ahb_clk(void)
> > +{
> > +       uint32_t freq, div, reg;
> > +
> > +       freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> > +
> > +       reg = __raw_readl(&mxc_ccm->cbcdr);
> > +       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
> > +                       MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
> > +
> > +       return freq / div;
> > +}
> 
> This is not correct, ahb clock is not fixed-source from PLL2.
> 
> Currently implementation,we did not take care the ahb_bypass clock setting
> and don't consider the lp-apm mode for main-bus clock input.

There is no "current implementation". Besides, that's how the BootROM sets it up 
so until someone needs it, this is ok.

> 
> Jason Liu