From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 30 Sep 2011 22:24:43 +0200 Subject: [U-Boot] [PATCH] x86: turn off cache: set control register properly In-Reply-To: <1317407227-8864-1-git-send-email-ondra.cap@gmail.com> References: <1317407227-8864-1-git-send-email-ondra.cap@gmail.com> Message-ID: <201109302224.43352.marek.vasut@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Friday, September 30, 2011 08:27:07 PM Ondrej Kupka wrote: > Bits should be ORed when they are supposed to be added together > > Cc: Graeme Russ > Signed-off-by: Ondrej Kupka > --- > arch/x86/cpu/start16.S | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S > index 3d3017a..9dabff2 100644 > --- a/arch/x86/cpu/start16.S > +++ b/arch/x86/cpu/start16.S > @@ -50,7 +50,7 @@ board_init16_ret: > > /* Turn of cache (this might require a 486-class CPU) */ > movl %cr0, %eax > - orl $(X86_CR0_NW & X86_CR0_CD), %eax > + orl $(X86_CR0_NW | X86_CR0_CD), %eax > movl %eax, %cr0 > wbinvd Dear Ondrej Kupka, Can we make this into some macro so we'd avoid such errors in the future ? Cheers