* [U-Boot] [PATCH 01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 02/12] m68k: " Anton Staaf
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee
---
arch/arm/include/asm/cache.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index d0518be..eef6a5a 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
void l2_cache_enable(void);
void l2_cache_disable(void);
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 64
+#endif
+
#endif /* _ASM_CACHE_H */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 02/12] m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 03/12] nios2: " Anton Staaf
` (11 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
Change-Id: Ica2b7459b7a61b521116eb23dc911451b4c2a9a5
---
arch/m68k/include/asm/cache.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 7c84e48..5c9bb30 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -207,4 +207,14 @@ void dcache_invalid(void);
#endif
+/*
+ * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
+ * alignment unless the board configuration has specified a new value.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 16
+#endif
+
#endif /* __CACHE_H */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 03/12] nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 02/12] m68k: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 04/12] powerpc: " Anton Staaf
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
Change-Id: I2982360f1c2ad9e8549d5b9ecdbb423d34b75157
---
arch/nios2/include/asm/cache.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h
index c78f343..2cc16e4 100644
--- a/arch/nios2/include/asm/cache.h
+++ b/arch/nios2/include/asm/cache.h
@@ -27,4 +27,15 @@
extern void flush_dcache (unsigned long start, unsigned long size);
extern void flush_icache (unsigned long start, unsigned long size);
+/*
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
+ * bytes. If the board configuration has not specified one we default to the
+ * largest of these values for alignment of DMA buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
#endif /* __ASM_NIOS2_CACHE_H_ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 04/12] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (2 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 03/12] nios2: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-13 6:23 ` Stefan Roese
2011-10-12 21:01 ` [U-Boot] [PATCH 05/12] sh: " Anton Staaf
` (9 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Change-Id: I5a007a515ef16e77003aaa74f9295ecc5104aa36
---
arch/powerpc/include/asm/cache.h | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05..e6b8f69 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -21,6 +21,12 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
#ifndef CONFIG_SYS_CACHELINE_SIZE
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 04/12] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 ` [U-Boot] [PATCH 04/12] powerpc: " Anton Staaf
@ 2011-10-13 6:23 ` Stefan Roese
0 siblings, 0 replies; 22+ messages in thread
From: Stefan Roese @ 2011-10-13 6:23 UTC (permalink / raw)
To: u-boot
On Wednesday 12 October 2011 23:01:43 Anton Staaf wrote:
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 05/12] sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (3 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 04/12] powerpc: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 06/12] sparc: " Anton Staaf
` (8 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Change-Id: I7dc5fb442b0e9173e9acdaf7acce3014c5b37625
---
arch/sh/include/asm/cache.h | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 2cfc0a7..6ffab4d 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -6,6 +6,7 @@
int cache_control(unsigned int cmd);
#define L1_CACHE_BYTES 32
+
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
@@ -30,6 +31,22 @@ void dcache_invalid_range(u32 start, u32 end)
: "m" (__m(v)));
}
}
+#else
+
+/*
+ * 32-bytes is the largest L1 data cache line size for SH the architecture. So
+ * it is a safe default for DMA alignment.
+ */
+#define ARCH_DMA_MINALIGN 32
+
#endif /* CONFIG_SH4 || CONFIG_SH4A */
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on SH.
+ */
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+#endif
+
#endif /* __ASM_SH_CACHE_H */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 06/12] sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (4 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 05/12] sh: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 07/12] avr32: " Anton Staaf
` (7 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Change-Id: If33383ff88e0555204c4ed1534d3961587fdee3a
---
arch/sparc/include/asm/cache.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 03e8d94..44870e8 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -28,4 +28,14 @@
#include <linux/config.h>
#include <asm/processor.h>
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
+ * use 32-bytes, the cacheline size for Sparc.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
#endif
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 07/12] avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (5 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 06/12] sparc: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 08/12] blackfin: " Anton Staaf
` (6 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Change-Id: I5965f64804c3938823be716f45298f093871fe83
---
arch/avr32/include/asm/cache.h | 40 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
create mode 100644 arch/avr32/include/asm/cache.h
diff --git a/arch/avr32/include/asm/cache.h b/arch/avr32/include/asm/cache.h
new file mode 100644
index 0000000..3b2b032
--- /dev/null
+++ b/arch/avr32/include/asm/cache.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AVR32_CACHE_H__
+#define __AVR32_CACHE_H__
+
+/*
+ * Since the AVR32 architecture has a queryable cacheline size with a maximum
+ * value of 256 we set the DMA buffer alignemnt requirement to this maximum
+ * value. The board config can override this if it knows that the cacheline
+ * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
+ * macro to specify cache line size, so if it is set we use it instead.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#elif defined(CONFIG_SYS_DCACHE_LINESZ)
+#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ
+#else
+#define ARCH_DMA_MINALIGN 256
+#endif
+
+#endif /* __AVR32_CACHE_H__ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (6 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 07/12] avr32: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 23:23 ` Mike Frysinger
2011-10-13 0:54 ` [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE Mike Frysinger
2011-10-12 21:01 ` [U-Boot] [PATCH 09/12] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Anton Staaf
` (5 subsequent siblings)
13 siblings, 2 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Change-Id: Ibdc2483c66c50d698108b790dd204fae38c7cb48
---
arch/blackfin/include/asm/cache.h | 36 ++++++++++++++++++++++++++++++++++++
1 files changed, 36 insertions(+), 0 deletions(-)
create mode 100644 arch/blackfin/include/asm/cache.h
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 0000000..f166c29
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_CACHE_H__
+#define __BLACKFIN_CACHE_H__
+
+/*
+ * The blackfin architecture has a 32-byte L1 data cache line size. Unless the
+ * board configuration has overridden this value we use it for aligning DMA
+ * buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
+#endif /* __BLACKFIN_CACHE_H__ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 ` [U-Boot] [PATCH 08/12] blackfin: " Anton Staaf
@ 2011-10-12 23:23 ` Mike Frysinger
2011-10-12 23:31 ` Anton Staaf
2011-10-13 0:54 ` [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE Mike Frysinger
1 sibling, 1 reply; 22+ messages in thread
From: Mike Frysinger @ 2011-10-12 23:23 UTC (permalink / raw)
To: u-boot
i'm just going to import Blackfin's asm/cache.h from Linux and define
CONFIG_SYS_CACHELINE_SIZE in Blackfin's asm/config.h
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111012/e529cfec/attachment.pgp
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 23:23 ` Mike Frysinger
@ 2011-10-12 23:31 ` Anton Staaf
0 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 23:31 UTC (permalink / raw)
To: u-boot
On Wed, Oct 12, 2011 at 4:23 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> i'm just going to import Blackfin's asm/cache.h from Linux and define
> CONFIG_SYS_CACHELINE_SIZE in Blackfin's asm/config.h
OK, how would you like to deal with that with respect to this patch set?
Would you like to do that and have me remove the blackfin patch?
Thanks,
Anton
> -mike
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE
2011-10-12 21:01 ` [U-Boot] [PATCH 08/12] blackfin: " Anton Staaf
2011-10-12 23:23 ` Mike Frysinger
@ 2011-10-13 0:54 ` Mike Frysinger
2011-10-13 2:31 ` Anton Staaf
1 sibling, 1 reply; 22+ messages in thread
From: Mike Frysinger @ 2011-10-13 0:54 UTC (permalink / raw)
To: u-boot
Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
arch/blackfin/include/asm/blackfin_local.h | 1 +
arch/blackfin/include/asm/cache.h | 70 ++++++++++++++++++++++++++++
arch/blackfin/include/asm/config.h | 3 +
3 files changed, 74 insertions(+), 0 deletions(-)
create mode 100644 arch/blackfin/include/asm/cache.h
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 27034d3..71207b6 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -49,6 +49,7 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#include <asm/linkage.h>
+#include <asm/cache.h>
#ifndef __ASSEMBLY__
# ifdef SHARED_RESOURCES
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 0000000..482e4b5
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_BLACKFIN_CACHE_H
+#define __ARCH_BLACKFIN_CACHE_H
+
+#include <asm/linkage.h> /* for asmlinkage */
+
+/*
+ * Bytes per L1 cache line
+ * Blackfin loads 32 bytes for cache
+ */
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+#ifdef CONFIG_SMP
+#define __cacheline_aligned
+#else
+#define ____cacheline_aligned
+
+/*
+ * Put cacheline_aliged data to L1 data memory
+ */
+#ifdef CONFIG_CACHELINE_ALIGNED_L1
+#define __cacheline_aligned \
+ __attribute__((__aligned__(L1_CACHE_BYTES), \
+ __section__(".data_l1.cacheline_aligned")))
+#endif
+
+#endif
+
+/*
+ * largest L1 which this arch supports
+ */
+#define L1_CACHE_SHIFT_MAX 5
+
+#if defined(CONFIG_SMP) && \
+ !defined(CONFIG_BFIN_CACHE_COHERENT)
+# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
+# define __ARCH_SYNC_CORE_ICACHE
+# endif
+# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
+# define __ARCH_SYNC_CORE_DCACHE
+# endif
+#ifndef __ASSEMBLY__
+asmlinkage void __raw_smp_mark_barrier_asm(void);
+asmlinkage void __raw_smp_check_barrier_asm(void);
+
+static inline void smp_mark_barrier(void)
+{
+ __raw_smp_mark_barrier_asm();
+}
+static inline void smp_check_barrier(void)
+{
+ __raw_smp_check_barrier_asm();
+}
+
+void resync_core_dcache(void);
+void resync_core_icache(void);
+#endif
+#endif
+
+
+#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 53af310..1a8de49 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -21,6 +21,9 @@
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
+/* U-Boot wants this config name */
+#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
+
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
--
1.7.6.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE
2011-10-13 0:54 ` [U-Boot] [PATCH] Blackfin: define CONFIG_SYS_CACHELINE_SIZE Mike Frysinger
@ 2011-10-13 2:31 ` Anton Staaf
0 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-13 2:31 UTC (permalink / raw)
To: u-boot
On Wed, Oct 12, 2011 at 5:54 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> Common U-Boot API wants this define, so import asm/cache.h from Linux
> to provide suitable defines.
>
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> ---
> ?arch/blackfin/include/asm/blackfin_local.h | ? ?1 +
> ?arch/blackfin/include/asm/cache.h ? ? ? ? ?| ? 70 ++++++++++++++++++++++++++++
> ?arch/blackfin/include/asm/config.h ? ? ? ? | ? ?3 +
> ?3 files changed, 74 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/blackfin/include/asm/cache.h
>
> diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
> index 27034d3..71207b6 100644
> --- a/arch/blackfin/include/asm/blackfin_local.h
> +++ b/arch/blackfin/include/asm/blackfin_local.h
> @@ -49,6 +49,7 @@
> ?#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
>
> ?#include <asm/linkage.h>
> +#include <asm/cache.h>
>
> ?#ifndef __ASSEMBLY__
> ?# ifdef SHARED_RESOURCES
> diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
> new file mode 100644
> index 0000000..482e4b5
> --- /dev/null
> +++ b/arch/blackfin/include/asm/cache.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright 2004-2009 Analog Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +
> +#ifndef __ARCH_BLACKFIN_CACHE_H
> +#define __ARCH_BLACKFIN_CACHE_H
> +
> +#include <asm/linkage.h> ? ? ? /* for asmlinkage */
> +
> +/*
> + * Bytes per L1 cache line
> + * Blackfin loads 32 bytes for cache
> + */
> +#define L1_CACHE_SHIFT 5
> +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
> +#define SMP_CACHE_BYTES ? ? ? ?L1_CACHE_BYTES
> +
> +#define ARCH_DMA_MINALIGN ? ? ?L1_CACHE_BYTES
> +
> +#ifdef CONFIG_SMP
> +#define __cacheline_aligned
> +#else
> +#define ____cacheline_aligned
> +
> +/*
> + * Put cacheline_aliged data to L1 data memory
> + */
> +#ifdef CONFIG_CACHELINE_ALIGNED_L1
> +#define __cacheline_aligned ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? __attribute__((__aligned__(L1_CACHE_BYTES), ? \
> + ? ? ? ? ? ? ? __section__(".data_l1.cacheline_aligned")))
> +#endif
> +
> +#endif
> +
> +/*
> + * largest L1 which this arch supports
> + */
> +#define L1_CACHE_SHIFT_MAX ? ? 5
> +
> +#if defined(CONFIG_SMP) && \
> + ? ?!defined(CONFIG_BFIN_CACHE_COHERENT)
> +# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
> +# define __ARCH_SYNC_CORE_ICACHE
> +# endif
> +# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
> +# define __ARCH_SYNC_CORE_DCACHE
> +# endif
> +#ifndef __ASSEMBLY__
> +asmlinkage void __raw_smp_mark_barrier_asm(void);
> +asmlinkage void __raw_smp_check_barrier_asm(void);
> +
> +static inline void smp_mark_barrier(void)
> +{
> + ? ? ? __raw_smp_mark_barrier_asm();
> +}
> +static inline void smp_check_barrier(void)
> +{
> + ? ? ? __raw_smp_check_barrier_asm();
> +}
> +
> +void resync_core_dcache(void);
> +void resync_core_icache(void);
> +#endif
> +#endif
> +
> +
> +#endif
> diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
> index 53af310..1a8de49 100644
> --- a/arch/blackfin/include/asm/config.h
> +++ b/arch/blackfin/include/asm/config.h
> @@ -21,6 +21,9 @@
> ?# define CONFIG_BFIN_SCRATCH_REG retn
> ?#endif
>
> +/* U-Boot wants this config name */
> +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
> +
> ?/* Make sure the structure is properly aligned */
> ?#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
> ?# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
> --
> 1.7.6.1
>
>
Acked-by: Anton Staaf <robotboy@chromium.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 09/12] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (7 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 08/12] blackfin: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 10/12] mips: " Anton Staaf
` (4 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
Change-Id: I8ee488ae0654cebac34f4d65771b4a8edbadf6fd
---
arch/microblaze/include/asm/cache.h | 37 +++++++++++++++++++++++++++++++++++
1 files changed, 37 insertions(+), 0 deletions(-)
create mode 100644 arch/microblaze/include/asm/cache.h
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
new file mode 100644
index 0000000..0373e88
--- /dev/null
+++ b/arch/microblaze/include/asm/cache.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MICROBLAZE_CACHE_H__
+#define __MICROBLAZE_CACHE_H__
+
+/*
+ * The microblaze can have either a 4 or 16 byte cacheline depending on whether
+ * you are using OPB(4) or CacheLink(16). If the board config has not specified
+ * a cacheline size we assume the larger value of 16 bytes for DMA buffer
+ * alignment.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 16
+#endif
+
+#endif /* __MICROBLAZE_CACHE_H__ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 10/12] mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (8 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 09/12] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 11/12] x86: " Anton Staaf
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Change-Id: Ia6cc9a950e0452926abf39867a70ec3910fbd1dd
---
arch/mips/include/asm/cache.h | 36 ++++++++++++++++++++++++++++++++++++
1 files changed, 36 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/cache.h
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 0000000..5406d5d
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIPS_CACHE_H__
+#define __MIPS_CACHE_H__
+
+/*
+ * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
+ * that as a default for aligning DMA buffers unless the board config has
+ * specified another cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 128
+#endif
+
+#endif /* __MIPS_CACHE_H__ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 11/12] x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (9 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 10/12] mips: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 21:01 ` [U-Boot] [PATCH 12/12] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition Anton Staaf
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Graeme Russ <graeme.russ@gmail.com>
Change-Id: Ib4b497910f674904f5fd0d9557a082d661c248bb
---
arch/x86/include/asm/cache.h | 35 +++++++++++++++++++++++++++++++++++
1 files changed, 35 insertions(+), 0 deletions(-)
create mode 100644 arch/x86/include/asm/cache.h
diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
new file mode 100644
index 0000000..87c9e0b
--- /dev/null
+++ b/arch/x86/include/asm/cache.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __X86_CACHE_H__
+#define __X86_CACHE_H__
+
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
+ * use 64-bytes, a safe default for x86.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 64
+#endif
+
+#endif /* __X86_CACHE_H__ */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 12/12] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (10 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 11/12] x86: " Anton Staaf
@ 2011-10-12 21:01 ` Anton Staaf
2011-10-12 22:19 ` [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
2011-10-13 3:47 ` Kumar Gala
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 21:01 UTC (permalink / raw)
To: u-boot
ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are
aligned correctly. In all current cases this means that the DMA
buffer will be aligned to at least the L1 data cache line size of
the configured architecture. If the board configuration file
does not specify the architecture L1 data cache line size then the
maximum line size of the architecture is used to align DMA buffers.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Laurence Withers <lwithers@guralp.com>
Change-Id: I6cc14dbc4b8fce3e4820e7b3ad3a06d1f2100152
---
include/common.h | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/include/common.h b/include/common.h
index eb19a44..74e41d4 100644
--- a/include/common.h
+++ b/include/common.h
@@ -814,6 +814,14 @@ int cpu_release(int nr, int argc, char * const argv[]);
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
/* Pull in stuff for the build system */
#ifdef DO_DEPS_ONLY
# include <environment.h>
--
1.7.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (11 preceding siblings ...)
2011-10-12 21:01 ` [U-Boot] [PATCH 12/12] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition Anton Staaf
@ 2011-10-12 22:19 ` Anton Staaf
2011-10-13 3:47 ` Kumar Gala
13 siblings, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-12 22:19 UTC (permalink / raw)
To: u-boot
Shoot, I just noticed that I forgot to purge the Gerrit generated Change-Id:
tags from the commit messages. If and when I send a v2 series I'll
remove these.
Thanks,
Anton
On Wed, Oct 12, 2011 at 2:01 PM, Anton Staaf <robotboy@chromium.org> wrote:
> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. ?It is
> used to define the minimum alignement requirement for a DMA buffer. ?This
> series of patches ensures that it will always be defined in the arch specific
> asm/cache.h header and that asm/cache.h is included in common.h. ?I chose to
> add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
> reasons. ?First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
> and thus to use it I would have to first define it correctly for all used
> architectures. ?I wasn't quite up to that task right now. ?Defining
> ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
> allow it to be the maximum cacheline size known for an architecture. ?And
> secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
> to align DMA buffers. ?In particular, on cache coherent architectures you can
> define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
> such as PCI alignment requirements).
>
> This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
> modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE. ?I will
> repost those patches based on this set shortly.
>
> I have included a lot of people on CC in individual patches to double check my
> work for each architecture.
>
> I have only been able to MAKEALL for arm currently. ?I installed the eldk tools
> for PowerPC, but ran into a problem building with them:
>
> cc1: error: Do not use -Os option if --enable-target-optspace is not set.
>
> So Tested-by's would be greatly appreciated.
>
> Thanks,
> ? ?Anton
>
> Anton Staaf (12):
> ?arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
>
> ?arch/arm/include/asm/cache.h ? ? ? ?| ? 11 +++++++++
> ?arch/avr32/include/asm/cache.h ? ? ?| ? 40 +++++++++++++++++++++++++++++++++++
> ?arch/blackfin/include/asm/cache.h ? | ? 36 +++++++++++++++++++++++++++++++
> ?arch/m68k/include/asm/cache.h ? ? ? | ? 10 ++++++++
> ?arch/microblaze/include/asm/cache.h | ? 37 ++++++++++++++++++++++++++++++++
> ?arch/mips/include/asm/cache.h ? ? ? | ? 36 +++++++++++++++++++++++++++++++
> ?arch/nios2/include/asm/cache.h ? ? ?| ? 11 +++++++++
> ?arch/powerpc/include/asm/cache.h ? ?| ? ?6 +++++
> ?arch/sh/include/asm/cache.h ? ? ? ? | ? 17 ++++++++++++++
> ?arch/sparc/include/asm/cache.h ? ? ?| ? 10 ++++++++
> ?arch/x86/include/asm/cache.h ? ? ? ?| ? 35 ++++++++++++++++++++++++++++++
> ?include/common.h ? ? ? ? ? ? ? ? ? ?| ? ?8 +++++++
> ?12 files changed, 257 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/avr32/include/asm/cache.h
> ?create mode 100644 arch/blackfin/include/asm/cache.h
> ?create mode 100644 arch/microblaze/include/asm/cache.h
> ?create mode 100644 arch/mips/include/asm/cache.h
> ?create mode 100644 arch/x86/include/asm/cache.h
>
> --
> 1.7.3.1
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures
2011-10-12 21:01 [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
` (12 preceding siblings ...)
2011-10-12 22:19 ` [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures Anton Staaf
@ 2011-10-13 3:47 ` Kumar Gala
2011-10-13 4:56 ` Mike Frysinger
2011-10-13 17:07 ` Anton Staaf
13 siblings, 2 replies; 22+ messages in thread
From: Kumar Gala @ 2011-10-13 3:47 UTC (permalink / raw)
To: u-boot
On Oct 12, 2011, at 4:01 PM, Anton Staaf wrote:
> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. It is
> used to define the minimum alignement requirement for a DMA buffer. This
> series of patches ensures that it will always be defined in the arch specific
> asm/cache.h header and that asm/cache.h is included in common.h. I chose to
> add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
> reasons. First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
> and thus to use it I would have to first define it correctly for all used
> architectures. I wasn't quite up to that task right now. Defining
> ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
> allow it to be the maximum cacheline size known for an architecture. And
> secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
> to align DMA buffers. In particular, on cache coherent architectures you can
> define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
> such as PCI alignment requirements).
>
> This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
> modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE. I will
> repost those patches based on this set shortly.
I haven't looked at this patchset you reference, but what is causing the need for buffer alignment?
I question if on PPC we really need this to be at a cache line granularity.
- k
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures
2011-10-13 3:47 ` Kumar Gala
@ 2011-10-13 4:56 ` Mike Frysinger
2011-10-13 17:07 ` Anton Staaf
1 sibling, 0 replies; 22+ messages in thread
From: Mike Frysinger @ 2011-10-13 4:56 UTC (permalink / raw)
To: u-boot
On Wednesday 12 October 2011 23:47:02 Kumar Gala wrote:
> I haven't looked at this patchset you reference, but what is causing the
> need for buffer alignment?
>
> I question if on PPC we really need this to be at a cache line granularity.
look at the "Add cache line alignment support" patchset
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111013/eb65ca57/attachment.pgp
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures
2011-10-13 3:47 ` Kumar Gala
2011-10-13 4:56 ` Mike Frysinger
@ 2011-10-13 17:07 ` Anton Staaf
1 sibling, 0 replies; 22+ messages in thread
From: Anton Staaf @ 2011-10-13 17:07 UTC (permalink / raw)
To: u-boot
On Wed, Oct 12, 2011 at 8:47 PM, Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Oct 12, 2011, at 4:01 PM, Anton Staaf wrote:
>
>> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. ?It is
>> used to define the minimum alignement requirement for a DMA buffer. ?This
>> series of patches ensures that it will always be defined in the arch specific
>> asm/cache.h header and that asm/cache.h is included in common.h. ?I chose to
>> add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
>> reasons. ?First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
>> and thus to use it I would have to first define it correctly for all used
>> architectures. ?I wasn't quite up to that task right now. ?Defining
>> ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
>> allow it to be the maximum cacheline size known for an architecture. ?And
>> secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
>> to align DMA buffers. ?In particular, on cache coherent architectures you can
>> define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
>> such as PCI alignment requirements).
>>
>> This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
>> modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE. ?I will
>> repost those patches based on this set shortly.
>
> I haven't looked at this patchset you reference, but what is causing the need for buffer alignment?
>
> I question if on PPC we really need this to be at a cache line granularity.
Briefly, if your cache architecture is not coherent with respect to
DMA transactions
then you need to flush and invalidate the cache before and after read
and write DMA
operations.
To safely do this you need the region that you wish to invalidate
and/or flush to
be aligned with the cache line at both ends. If it is not then you
run the risk of
corrupting variables that are in the unaligned memory at either end of
the buffer.
So, in short, if the PowerPC cache architecture is coherent with
respect to memory
access done by other bus masters then you can set this value to 1. If
it is not,
then you must set it to at least the cache line size.
Thanks,
Anton
> - k
^ permalink raw reply [flat|nested] 22+ messages in thread