* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
@ 2011-10-04 9:13 eibach at gdsys.de
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip eibach at gdsys.de
` (5 more replies)
0 siblings, 6 replies; 19+ messages in thread
From: eibach at gdsys.de @ 2011-10-04 9:13 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
drivers/gpio/Makefile | 1 +
drivers/gpio/pca9698.c | 123 ++++++++++++++++++++++++++++++++++++++++++++++++
include/pca9698.h | 9 ++++
3 files changed, 133 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/pca9698.c
create mode 100644 include/pca9698.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..38a62c3 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
+COBJS-$(CONFIG_PCA9698) += pca9698.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c
new file mode 100644
index 0000000..b946efa
--- /dev/null
+++ b/drivers/gpio/pca9698.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Driver for NXP's pca9698 40 bit I2C gpio expander
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <pca9698.h>
+
+/*
+ * The pca9698 registers
+ */
+
+#define PCA9698_REG_INPUT 0x00
+#define PCA9698_REG_OUTPUT 0x08
+#define PCA9698_REG_POLARITY 0x10
+#define PCA9698_REG_CONFIG 0x18
+
+#define PCA9698_BUFFER_SIZE 5
+
+static int pca9698_read40(u8 chip, u8 offset, u8 *buffer)
+{
+ u8 command = offset | 0x80; /* autoincrement */
+
+ return i2c_read(chip, command, 1, buffer, PCA9698_BUFFER_SIZE);
+}
+
+static int pca9698_write40(u8 chip, u8 offset, u8 *buffer)
+{
+ u8 command = offset | 0x80; /* autoincrement */
+
+ return i2c_write(chip, command, 1, buffer, PCA9698_BUFFER_SIZE);
+}
+
+static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value)
+{
+ unsigned byte = gpio / 8;
+ unsigned bit = gpio % 8;
+
+ if (value)
+ buffer[byte] |= (1 << bit);
+ else
+ buffer[byte] &= ~(1 << bit);
+}
+
+int pca9698_direction_input(u8 chip, unsigned offset)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(chip, PCA9698_REG_CONFIG, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(offset, data, 1);
+ return pca9698_write40(chip, PCA9698_REG_CONFIG, data);
+}
+
+int pca9698_direction_output(u8 chip, unsigned offset)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(chip, PCA9698_REG_CONFIG, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(offset, data, 0);
+ return pca9698_write40(chip, PCA9698_REG_CONFIG, data);
+}
+
+int pca9698_get_input(u8 chip, unsigned offset)
+{
+ unsigned config_byte = offset / 8;
+ unsigned config_bit = offset % 8;
+ unsigned value;
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(chip, PCA9698_REG_INPUT, data);
+ if (res)
+ return -1;
+
+ value = data[config_byte] & (1 << config_bit);
+
+ return !!value;
+}
+
+int pca9698_set_output(u8 chip, unsigned offset, int value)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(chip, PCA9698_REG_OUTPUT, data);
+ if (res)
+ return res;
+
+ memset(data, sizeof(data), 0);
+ pca9698_set_bit(offset, data, value);
+ return pca9698_write40(chip, PCA9698_REG_OUTPUT, data);
+}
diff --git a/include/pca9698.h b/include/pca9698.h
new file mode 100644
index 0000000..2506088
--- /dev/null
+++ b/include/pca9698.h
@@ -0,0 +1,9 @@
+#ifndef __PCA9698_H_
+#define __PCA9698_H_
+
+int pca9698_direction_input(u8 chip, unsigned offset);
+int pca9698_direction_output(u8 chip, unsigned offset);
+int pca9698_get_input(u8 chip, unsigned offset);
+int pca9698_set_output(u8 chip, unsigned offset, int value);
+
+#endif /* __PCA9698_H_ */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
@ 2011-10-04 9:13 ` eibach at gdsys.de
2011-10-12 9:49 ` Stefan Roese
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g eibach at gdsys.de
` (4 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: eibach at gdsys.de @ 2011-10-04 9:13 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <eibach@gdsys.de>
Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be
stopped with well defined keypresses.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
include/configs/intip.h | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 3ff4a86..931a43f 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
-#define CONFIG_IDENT_STRING " devconcenter 0.02"
+#define CONFIG_IDENT_STRING " devconcenter 0.03"
#else
#define CONFIG_HOSTNAME intip
-#define CONFIG_IDENT_STRING " intip 0.02"
+#define CONFIG_IDENT_STRING " intip 0.03"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
@@ -63,6 +63,10 @@
#define CONFIG_FIT
#define CFG_ALT_MEMTEST
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip eibach at gdsys.de
@ 2011-10-04 9:13 ` eibach at gdsys.de
2011-10-12 9:50 ` Stefan Roese
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Add Io64 board support eibach at gdsys.de
` (3 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: eibach at gdsys.de @ 2011-10-04 9:13 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <eibach@gdsys.de>
Fan PWM lookuptable was modified to start at 46 degrees
celsius instead of 40 degrees celsius.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
include/configs/dlvision-10g.h | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 4fc5262..1468197 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -34,7 +34,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
@@ -117,8 +117,8 @@
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
- { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+ { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
+ { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
/* EBC peripherals */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Add Io64 board support
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip eibach at gdsys.de
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g eibach at gdsys.de
@ 2011-10-04 9:13 ` eibach at gdsys.de
2011-10-06 21:09 ` Wolfgang Denk
2011-10-06 21:10 ` Wolfgang Denk
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip eibach at gdsys.de
` (2 subsequent siblings)
5 siblings, 2 replies; 19+ messages in thread
From: eibach at gdsys.de @ 2011-10-04 9:13 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <eibach@gdsys.de>
Board support for the Guntermann & Drunck Io64.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
arch/powerpc/lib/board.c | 7 +
board/gdsys/405ex/405ex.c | 250 +++++++++++++++++
board/gdsys/405ex/405ex.h | 10 +
board/gdsys/405ex/Makefile | 53 ++++
board/gdsys/405ex/chip_config.c | 96 +++++++
board/gdsys/405ex/io64.c | 381 ++++++++++++++++++++++++++
board/gdsys/common/Makefile | 1 +
board/gdsys/common/miiphybb.c | 58 ++++-
boards.cfg | 1 +
include/configs/io64.h | 565 +++++++++++++++++++++++++++++++++++++++
include/gdsys_fpga.h | 19 ++
11 files changed, 1433 insertions(+), 8 deletions(-)
create mode 100644 board/gdsys/405ex/405ex.c
create mode 100644 board/gdsys/405ex/405ex.h
create mode 100644 board/gdsys/405ex/Makefile
create mode 100644 board/gdsys/405ex/chip_config.c
create mode 100644 board/gdsys/405ex/io64.c
create mode 100644 include/configs/io64.h
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 9885b14..1be0a34 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -130,6 +130,10 @@ ulong monitor_flash_len;
#include <bedbug/type.h>
#endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+#include <gdsys_fpga.h>
+#endif
+
/************************************************************************
* Utilities *
************************************************************************
@@ -322,6 +326,9 @@ init_fnc_t *init_sequence[] = {
#ifdef CONFIG_POST
post_init_f,
#endif
+#ifdef CONFIG_FPGA_INIT
+ init_func_fpga,
+#endif
INIT_FUNC_WATCHDOG_RESET
init_func_ram,
#if defined(CONFIG_SYS_DRAM_TEST)
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
new file mode 100644
index 0000000..a0d8a2e
--- /dev/null
+++ b/board/gdsys/405ex/405ex.c
@@ -0,0 +1,250 @@
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include <gdsys_fpga.h>
+
+#include "405ex.h"
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ */
+ val = SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int init_func_fpga(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ gd405ex_init();
+
+ gd405ex_set_fpga_reset(1);
+
+ gd405ex_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!gd405ex_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ gd405ex_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+ u16 *reflection_target = &fpga->reflection_low;
+#else
+ u16 *reflection_target = &fpga->reflection_high;
+#endif
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ out_le16(&fpga->reflection_low,
+ REFLECTION_TESTPATTERN);
+
+ if (in_le16(reflection_target) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h
new file mode 100644
index 0000000..b15623f
--- /dev/null
+++ b/board/gdsys/405ex/405ex.h
@@ -0,0 +1,10 @@
+#ifndef __405EX_H_
+#define __405EX_H_
+
+/* functions to be provided by board implementation */
+void gd405ex_init(void);
+void gd405ex_set_fpga_reset(unsigned state);
+void gd405ex_setup_hw(void);
+int gd405ex_get_fpga_done(unsigned fpga);
+
+#endif /* __405EX_H_ */
diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile
new file mode 100644
index 0000000..4549705
--- /dev/null
+++ b/board/gdsys/405ex/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_IO64) += io64.o
+
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+
+COBJS := $(BOARD).o $(COBJS-y)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c
new file mode 100644
index 0000000..12cb3bf
--- /dev/null
+++ b/board/gdsys/405ex/chip_config.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
new file mode 100644
index 0000000..4eeb15b
--- /dev/null
+++ b/board/gdsys/405ex/io64.c
@@ -0,0 +1,381 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * based on kilauea.c
+ * by Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <pca9698.h>
+
+#include "405ex.h"
+#include <gdsys_fpga.h>
+
+#include <miiphy.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
+#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+};
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static inline void blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
+
+/*
+ * Board early initialization function
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned dev)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
+ int fpga_state = get_fpga_state(dev);
+
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ printf("FPGA%d: ", dev);
+ if (fpga_state & FPGA_STATE_PLATFORM)
+ printf("(legacy) ");
+
+ if (fpga_state & FPGA_STATE_DONE_FAILED) {
+ printf(" done timed out\n");
+ return;
+ }
+
+ if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+ printf(" refelectione test failed\n");
+ return;
+ }
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: CATCenter Io64\n");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ return 0;
+}
+
+int configure_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch to powerdown */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value | 0x0004))
+ goto err_out;
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int verify_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* verify SGMII link status */
+ if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
+ goto err_out;
+ if (!(value & (1 << 10)))
+ return -2;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int last_stage_init(void)
+{
+ unsigned int k;
+ unsigned int fpga;
+ ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+ ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
+ int failed = 0;
+ char str_phys[] = "Setup PHYs -";
+ char str_serdes[] = "Start SERDES blocks";
+ char str_channels[] = "Start FPGA channels";
+ char str_locks[] = "Verify SERDES locks";
+ char str_status[] = "Verify PHY status -";
+ char slash[] = "\\|/-\\|/-";
+
+ print_fpga_info(0);
+ print_fpga_info(1);
+
+ /* setup Gbit PHYs */
+ puts("TRANS: ");
+ puts(str_phys);
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+
+ miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_phys));
+
+ /* take fpga serdes blocks out of reset */
+ puts(str_serdes);
+ udelay(500000);
+ out_le16(&fpga0->quad_serdes_reset, 0);
+ out_le16(&fpga1->quad_serdes_reset, 0);
+ blank_string(strlen(str_serdes));
+
+ /* take channels out of reset */
+ puts(str_channels);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
+ for (k = 0; k < 32; ++k)
+ out_le16(ch0_config_int + 4 * k, 0);
+ }
+ blank_string(strlen(str_channels));
+
+ /* verify channels serdes lock */
+ puts(str_locks);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
+ for (k = 0; k < 32; ++k) {
+ u16 status = in_le16(ch0_status_int + 4*k);
+ if (!(status & (1 << 4))) {
+ failed = 1;
+ printf("fpga %d channel %d: no serdes lock\n",
+ fpga, k);
+ }
+ /* reset events */
+ out_le16(ch0_status_int + 4*k, status);
+ }
+ }
+ blank_string(strlen(str_locks));
+
+ /* verify phy status */
+ puts(str_status);
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
+ printf("verify baseboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
+ printf("verify extensionboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_status));
+
+ printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
+
+ return 0;
+}
+
+void gd405ex_init(void)
+{
+ unsigned int k;
+
+ if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
+ } else {
+ pca9698_direction_output(0x22, 39);
+ }
+}
+
+void gd405ex_set_fpga_reset(unsigned state)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy) {
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+ } else {
+ pca9698_set_output(0x22, 39, state ? 0 : 1);
+ }
+}
+
+void gd405ex_setup_hw(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
+}
+
+int gd405ex_get_fpga_done(unsigned fpga)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy)
+ return in_le16((void *)LATCH3_BASE)
+ & CONFIG_SYS_FPGA_DONE(fpga);
+ else
+ return pca9698_get_input(0x22, fpga ? 9 : 8);
+}
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 4c7fc99..47f8c95 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -30,6 +30,7 @@ endif
LIB = $(obj)lib$(VENDOR).o
COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IO64) += miiphybb.o
COBJS-$(CONFIG_IOCON) += osd.o
COBJS-$(CONFIG_DLVISION_10G) += osd.o
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
index e56e966..46f1a1e 100644
--- a/board/gdsys/common/miiphybb.c
+++ b/board/gdsys/common/miiphybb.c
@@ -26,6 +26,11 @@
#include <asm/io.h>
+struct io_bb_pinset {
+ int mdio;
+ int mdc;
+};
+
static int io_bb_mii_init(struct bb_miiphy_bus *bus)
{
return 0;
@@ -33,47 +38,57 @@ static int io_bb_mii_init(struct bb_miiphy_bus *bus)
static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
{
+ struct io_bb_pinset *pins = bus->priv;
+
out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_TCR) | pins->mdio);
return 0;
}
static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
+ struct io_bb_pinset *pins = bus->priv;
+
out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_TCR) & ~pins->mdio);
return 0;
}
static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
+ struct io_bb_pinset *pins = bus->priv;
+
if (v)
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_OR) | pins->mdio);
else
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_OR) & ~pins->mdio);
return 0;
}
static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
- *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+ struct io_bb_pinset *pins = bus->priv;
+
+ *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
return 0;
}
static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
+ struct io_bb_pinset *pins = bus->priv;
+
if (v)
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+ in_be32((void *)GPIO0_OR) | pins->mdc);
else
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+ in_be32((void *)GPIO0_OR) & ~pins->mdc);
return 0;
}
@@ -85,6 +100,19 @@ static int io_bb_delay(struct bb_miiphy_bus *bus)
return 0;
}
+struct io_bb_pinset io_bb_pinsets[] = {
+ {
+ .mdio = CONFIG_SYS_MDIO_PIN,
+ .mdc = CONFIG_SYS_MDC_PIN,
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .mdio = CONFIG_SYS_MDIO1_PIN,
+ .mdc = CONFIG_SYS_MDC1_PIN,
+ },
+#endif
+};
+
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = CONFIG_SYS_GBIT_MII_BUSNAME,
@@ -95,7 +123,21 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
.get_mdio = io_bb_get_mdio,
.set_mdc = io_bb_set_mdc,
.delay = io_bb_delay,
- }
+ .priv = &io_bb_pinsets[0],
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ .priv = &io_bb_pinsets[1],
+ },
+#endif
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
diff --git a/boards.cfg b/boards.cfg
index d32ff7e..57ea36f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -838,6 +838,7 @@ dlvision-10g powerpc ppc4xx 405ep gdsys
gdppc440etx powerpc ppc4xx - gdsys
intip powerpc ppc4xx intip gdsys - intip:INTIB
io powerpc ppc4xx 405ep gdsys
+io64 powerpc ppc4xx 405ex gdsys
iocon powerpc ppc4xx 405ep gdsys
neo powerpc ppc4xx - gdsys
icon powerpc ppc4xx - mosaixtech
diff --git a/include/configs/io64.h b/include/configs/io64.h
new file mode 100644
index 0000000..64b8943
--- /dev/null
+++ b/include/configs/io64.h
@@ -0,0 +1,565 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * based on kilauea.h
+ * by Stefan Roese, DENX Software Engineering, sr at denx.de.
+ * and Grant Erickson <gerickson@nuovations.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_IO64 1 /* Board is Io64 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EX 1 /* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
+/*
+ * CHIP_21 errata
+ */
+#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME io64
+#define CONFIG_IDENT_STRING " io64 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_NVRAM_BASE 0xF0000000
+#define CONFIG_SYS_FPGA0_BASE 0xF0100000
+#define CONFIG_SYS_FPGA1_BASE 0xF0108000
+#define CONFIG_SYS_LATCH_BASE 0xF0200000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS 4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE \
+ (4 << 10) /* 4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR \
+ (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE 16
+# define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
+#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
+
+#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
+#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
+
+#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
+
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ * SDRAM Controller DDR autocalibration values and takes a lot longer
+ * to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
+ SDRAM_MCOPT1_4_BANKS | \
+ SDRAM_MCOPT1_DDR2_TYPE | \
+ SDRAM_MCOPT1_QDEP | \
+ SDRAM_MCOPT1_DCOO_DISABLED)
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
+ SDRAM_MODT_EB0R_ENABLE)
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
+ SDRAM_CODT_CKLZ_36OHM | \
+ SDRAM_CODT_DQS_1_8_V_DDR2 | \
+ SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(80) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
+ SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_75OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4 | \
+ JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(0x0) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
+ SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
+ SDRAM_DLCR_DLCS_CONT_DONE | \
+ SDRAM_DLCR_DLCV_ENCODE(165))
+#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
+ SDRAM_SDTR1_RTW_2_CLK | \
+ SDRAM_SDTR1_WTWO_1_CLK | \
+ SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
+ SDRAM_SDTR2_WTR_2_CLK | \
+ SDRAM_SDTR2_XSNR_32_CLK | \
+ SDRAM_SDTR2_WPC_4_CLK | \
+ SDRAM_SDTR2_RPC_2_CLK | \
+ SDRAM_SDTR2_RP_3_CLK | \
+ SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
+ SDRAM_SDTR3_RC_ENCODE(12) | \
+ SDRAM_SDTR3_XCS | \
+ SDRAM_SDTR3_RFC_ENCODE(21))
+#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
+ SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
+ SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
+ SDRAM_MEMODE_RTT_75OHM)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+
+#define CONFIG_PCA9698 1 /* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
+ { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0 1
+
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 0x13
+
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB "silent\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "logversion=2\0" \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+
+#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY_ON | \
+ CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_64MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (NVRAM/Uart) */
+#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT)
+
+/* Memory Bank 2 (FPGA) */
+#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(5) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+ (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+ (k ? 0x0040 : 0x0080)
+
+#define CONFIG_SYS_FPGA_COUNT 2
+#define CONFIG_FPGA_INIT
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 EBC_DATA_PAR(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_DATA_PAR(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_DATA_PAR(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 EBC_DATA_PAR(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 IRQ(6) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 UART0_DCD UART1_CTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 UART0_DSR UART1_RTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 UART0_CTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 UART0_RTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 UART0_DTR UART1_TX */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 UART0_RI UART1_RX */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 DMA_EOT1 IRQ(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 DMA_REQ1 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 DMA_ACK1 IRQ(0) */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
+
+#endif /* __CONFIG_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index c0b1b5c..e7a072b 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -24,9 +24,12 @@
#ifndef __GDSYS_FPGA_H
#define __GDSYS_FPGA_H
+int init_func_fpga(void);
+
enum {
FPGA_STATE_DONE_FAILED = 1 << 0,
FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+ FPGA_STATE_PLATFORM = 1 << 2,
};
int get_fpga_state(unsigned dev);
@@ -68,6 +71,22 @@ typedef struct ihs_fpga {
} ihs_fpga_t;
#endif
+#ifdef CONFIG_IO64
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_features; /* 0x0004 */
+ u16 fpga_version; /* 0x0006 */
+ u16 reserved_0[5]; /* 0x0008 */
+ u16 quad_serdes_reset; /* 0x0012 */
+ u16 reserved_1[502]; /* 0x0014 */
+ u16 ch0_status_int; /* 0x0400 */
+ u16 ch0_config_int; /* 0x0402 */
+ u16 reserved_2[7677]; /* 0x0404 */
+ u16 reflection_high; /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
#ifdef CONFIG_IOCON
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
` (2 preceding siblings ...)
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Add Io64 board support eibach at gdsys.de
@ 2011-10-04 9:13 ` eibach at gdsys.de
2011-10-12 9:50 ` Stefan Roese
2011-10-18 14:23 ` [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port Stefan Roese
2011-10-21 22:43 ` Wolfgang Denk
5 siblings, 1 reply; 19+ messages in thread
From: eibach at gdsys.de @ 2011-10-04 9:13 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <eibach@gdsys.de>
Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
include/configs/intip.h | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 931a43f..92b65af 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
-#define CONFIG_IDENT_STRING " devconcenter 0.03"
+#define CONFIG_IDENT_STRING " devconcenter 0.05"
#else
#define CONFIG_HOSTNAME intip
-#define CONFIG_IDENT_STRING " intip 0.03"
+#define CONFIG_IDENT_STRING " intip 0.05"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
@@ -200,13 +200,13 @@
#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542
+#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
@@ -216,11 +216,11 @@
#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823
+#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
-#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
+#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Add Io64 board support
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Add Io64 board support eibach at gdsys.de
@ 2011-10-06 21:09 ` Wolfgang Denk
2011-10-06 21:10 ` Wolfgang Denk
1 sibling, 0 replies; 19+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:09 UTC (permalink / raw)
To: u-boot
Dear eibach at gdsys.de,
In message <1317719635-2792-4-git-send-email-eibach@gdsys.de> you wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Board support for the Guntermann & Drunck Io64.
>
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
> arch/powerpc/lib/board.c | 7 +
> board/gdsys/405ex/405ex.c | 250 +++++++++++++++++
> board/gdsys/405ex/405ex.h | 10 +
> board/gdsys/405ex/Makefile | 53 ++++
> board/gdsys/405ex/chip_config.c | 96 +++++++
> board/gdsys/405ex/io64.c | 381 ++++++++++++++++++++++++++
> board/gdsys/common/Makefile | 1 +
> board/gdsys/common/miiphybb.c | 58 ++++-
> boards.cfg | 1 +
> include/configs/io64.h | 565 +++++++++++++++++++++++++++++++++++++++
> include/gdsys_fpga.h | 19 ++
> 11 files changed, 1433 insertions(+), 8 deletions(-)
> create mode 100644 board/gdsys/405ex/405ex.c
> create mode 100644 board/gdsys/405ex/405ex.h
> create mode 100644 board/gdsys/405ex/Makefile
> create mode 100644 board/gdsys/405ex/chip_config.c
> create mode 100644 board/gdsys/405ex/io64.c
> create mode 100644 include/configs/io64.h
Checkpatch says:
total: 3 errors, 58 warnings, 1538 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Work 8 hours, sleep 8 hours; but not the same 8 hours.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Add Io64 board support
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Add Io64 board support eibach at gdsys.de
2011-10-06 21:09 ` Wolfgang Denk
@ 2011-10-06 21:10 ` Wolfgang Denk
1 sibling, 0 replies; 19+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:10 UTC (permalink / raw)
To: u-boot
Dear eibach at gdsys.de,
In message <1317719635-2792-4-git-send-email-eibach@gdsys.de> you wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Board support for the Guntermann & Drunck Io64.
>
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
> arch/powerpc/lib/board.c | 7 +
> board/gdsys/405ex/405ex.c | 250 +++++++++++++++++
> board/gdsys/405ex/405ex.h | 10 +
> board/gdsys/405ex/Makefile | 53 ++++
> board/gdsys/405ex/chip_config.c | 96 +++++++
> board/gdsys/405ex/io64.c | 381 ++++++++++++++++++++++++++
> board/gdsys/common/Makefile | 1 +
> board/gdsys/common/miiphybb.c | 58 ++++-
> boards.cfg | 1 +
> include/configs/io64.h | 565 +++++++++++++++++++++++++++++++++++++++
> include/gdsys_fpga.h | 19 ++
> 11 files changed, 1433 insertions(+), 8 deletions(-)
> create mode 100644 board/gdsys/405ex/405ex.c
> create mode 100644 board/gdsys/405ex/405ex.h
> create mode 100644 board/gdsys/405ex/Makefile
> create mode 100644 board/gdsys/405ex/chip_config.c
> create mode 100644 board/gdsys/405ex/io64.c
> create mode 100644 include/configs/io64.h
Also, entry to MAINTAINERS missing.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
All I ask is a chance to prove that money can't make me happy.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip eibach at gdsys.de
@ 2011-10-12 9:49 ` Stefan Roese
0 siblings, 0 replies; 19+ messages in thread
From: Stefan Roese @ 2011-10-12 9:49 UTC (permalink / raw)
To: u-boot
On Tuesday 04 October 2011 11:13:52 eibach at gdsys.de wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be
> stopped with well defined keypresses.
Applied to u-boot-ppc4xx/master. Thanks.
Best regards,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g eibach at gdsys.de
@ 2011-10-12 9:50 ` Stefan Roese
0 siblings, 0 replies; 19+ messages in thread
From: Stefan Roese @ 2011-10-12 9:50 UTC (permalink / raw)
To: u-boot
On Tuesday 04 October 2011 11:13:53 eibach at gdsys.de wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Fan PWM lookuptable was modified to start at 46 degrees
> celsius instead of 40 degrees celsius.
Applied to u-boot-ppc4xx/master. Thanks.
Best regards,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip eibach at gdsys.de
@ 2011-10-12 9:50 ` Stefan Roese
0 siblings, 0 replies; 19+ messages in thread
From: Stefan Roese @ 2011-10-12 9:50 UTC (permalink / raw)
To: u-boot
On Tuesday 04 October 2011 11:13:55 eibach at gdsys.de wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Some intip boards don't seem to run stable with CL4, datasheets suggest
> that CL5 is the safe value.
Applied to u-boot-ppc4xx/master. Thanks.
Best regards,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
` (3 preceding siblings ...)
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip eibach at gdsys.de
@ 2011-10-18 14:23 ` Stefan Roese
2011-10-21 22:43 ` Wolfgang Denk
5 siblings, 0 replies; 19+ messages in thread
From: Stefan Roese @ 2011-10-18 14:23 UTC (permalink / raw)
To: u-boot
Hi Dirk,
On Tuesday 04 October 2011 11:13:51 eibach at gdsys.de wrote:
> From: Dirk Eibach <eibach@gdsys.de>
Checkpatch output:
ERROR: memset size is 3rd argument, not the second.
#239: FILE: drivers/gpio/pca9698.c:120:
+ memset(data, sizeof(data), 0);
total: 1 errors, 0 warnings, 139 lines checked
So, this now really is a good checkpatch feature. I wasn't ware, that it
checked for such bugs as well. Nice. :)
Please fix and resubmit.
Thanks,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
@ 2011-10-20 9:12 Dirk Eibach
2011-10-20 9:31 ` Stefan Roese
2011-10-23 19:01 ` Wolfgang Denk
0 siblings, 2 replies; 19+ messages in thread
From: Dirk Eibach @ 2011-10-20 9:12 UTC (permalink / raw)
To: u-boot
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
drivers/gpio/Makefile | 1 +
drivers/gpio/pca9698.c | 143 ++++++++++++++++++++++++++++++++++++++++++++++++
include/pca9698.h | 34 +++++++++++
3 files changed, 178 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/pca9698.c
create mode 100644 include/pca9698.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..38a62c3 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
+COBJS-$(CONFIG_PCA9698) += pca9698.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c
new file mode 100644
index 0000000..fe6d2c6
--- /dev/null
+++ b/drivers/gpio/pca9698.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Driver for NXP's pca9698 40 bit I2C gpio expander
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+#include <pca9698.h>
+
+/*
+ * The pca9698 registers
+ */
+
+#define PCA9698_REG_INPUT 0x00
+#define PCA9698_REG_OUTPUT 0x08
+#define PCA9698_REG_POLARITY 0x10
+#define PCA9698_REG_CONFIG 0x18
+
+#define PCA9698_BUFFER_SIZE 5
+#define PCA9698_GPIO_COUNT 40
+
+static int pca9698_read40(u8 addr, u8 offset, u8 *buffer)
+{
+ u8 command = offset | 0x80; /* autoincrement */
+
+ return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
+}
+
+static int pca9698_write40(u8 addr, u8 offset, u8 *buffer)
+{
+ u8 command = offset | 0x80; /* autoincrement */
+
+ return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
+}
+
+static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value)
+{
+ unsigned byte = gpio / 8;
+ unsigned bit = gpio % 8;
+
+ if (value)
+ buffer[byte] |= (1 << bit);
+ else
+ buffer[byte] &= ~(1 << bit);
+}
+
+int pca9698_request(unsigned gpio, const char *label)
+{
+ if (gpio >= PCA9698_GPIO_COUNT)
+ return -EINVAL;
+
+ return 0;
+}
+
+void pca9698_free(unsigned gpio)
+{
+}
+
+int pca9698_direction_input(u8 addr, unsigned gpio)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(gpio, data, 1);
+
+ return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
+}
+
+int pca9698_direction_output(u8 addr, unsigned gpio, int value)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_set_value(addr, gpio, value);
+ if (res)
+ return res;
+
+ res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(gpio, data, 0);
+
+ return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
+}
+
+int pca9698_get_value(u8 addr, unsigned gpio)
+{
+ unsigned config_byte = gpio / 8;
+ unsigned config_bit = gpio % 8;
+ unsigned value;
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(addr, PCA9698_REG_INPUT, data);
+ if (res)
+ return -1;
+
+ value = data[config_byte] & (1 << config_bit);
+
+ return !!value;
+}
+
+int pca9698_set_value(u8 addr, unsigned gpio, int value)
+{
+ u8 data[PCA9698_BUFFER_SIZE];
+ int res;
+
+ res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(gpio, data, value);
+
+ return pca9698_write40(addr, PCA9698_REG_OUTPUT, data);
+}
diff --git a/include/pca9698.h b/include/pca9698.h
new file mode 100644
index 0000000..67b364e
--- /dev/null
+++ b/include/pca9698.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PCA9698_H_
+#define __PCA9698_H_
+
+int pca9698_request(unsigned gpio, const char *label);
+void pca9698_free(unsigned gpio);
+int pca9698_direction_input(u8 addr, unsigned gpio);
+int pca9698_direction_output(u8 addr, unsigned gpio, int value);
+int pca9698_get_value(u8 addr, unsigned gpio);
+int pca9698_set_value(u8 addr, unsigned gpio, int value);
+
+#endif /* __PCA9698_H_ */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-20 9:12 Dirk Eibach
@ 2011-10-20 9:31 ` Stefan Roese
2011-10-20 9:40 ` Eibach, Dirk
2011-10-23 19:01 ` Wolfgang Denk
1 sibling, 1 reply; 19+ messages in thread
From: Stefan Roese @ 2011-10-20 9:31 UTC (permalink / raw)
To: u-boot
On Thursday 20 October 2011 11:12:20 Dirk Eibach wrote:
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Next time please update the patch version in the subject and add the changes
below the "---" line. Other than this:
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-20 9:31 ` Stefan Roese
@ 2011-10-20 9:40 ` Eibach, Dirk
0 siblings, 0 replies; 19+ messages in thread
From: Eibach, Dirk @ 2011-10-20 9:40 UTC (permalink / raw)
To: u-boot
> Next time please update the patch version in the subject and
> add the changes below the "---" line. Other than this:
Oops, wrong serialization of save / git-send-email. I did a resend.
Cheers
Dirk
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
` (4 preceding siblings ...)
2011-10-18 14:23 ` [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port Stefan Roese
@ 2011-10-21 22:43 ` Wolfgang Denk
5 siblings, 0 replies; 19+ messages in thread
From: Wolfgang Denk @ 2011-10-21 22:43 UTC (permalink / raw)
To: u-boot
Dear eibach at gdsys.de,
In message <1317719635-2792-1-git-send-email-eibach@gdsys.de> you wrote:
> From: Dirk Eibach <eibach@gdsys.de>
>
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
> drivers/gpio/Makefile | 1 +
> drivers/gpio/pca9698.c | 123 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/pca9698.h | 9 ++++
> 3 files changed, 133 insertions(+), 0 deletions(-)
> create mode 100644 drivers/gpio/pca9698.c
> create mode 100644 include/pca9698.h
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The reasonable man adapts himself to the world; the unreasonable one
persists in trying to adapt the world to himself. Therefore all
progress depends on the unreasonable man." - George Bernard Shaw
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-20 9:12 Dirk Eibach
2011-10-20 9:31 ` Stefan Roese
@ 2011-10-23 19:01 ` Wolfgang Denk
2011-10-26 6:44 ` Eibach, Dirk
1 sibling, 1 reply; 19+ messages in thread
From: Wolfgang Denk @ 2011-10-23 19:01 UTC (permalink / raw)
To: u-boot
Dear Dirk Eibach,
In message <1319101940-780-1-git-send-email-eibach@gdsys.de> you wrote:
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
> drivers/gpio/Makefile | 1 +
> drivers/gpio/pca9698.c | 143 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/pca9698.h | 34 +++++++++++
> 3 files changed, 178 insertions(+), 0 deletions(-)
> create mode 100644 drivers/gpio/pca9698.c
> create mode 100644 include/pca9698.h
is this some v3 of the patch? If so, where is the change log? What
has been changes?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There is is no reason for any individual to have a computer in their
home. -- Ken Olsen (President of Digital Equipment Corporation),
Convention of the World Future Society, in Boston, 1977
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-23 19:01 ` Wolfgang Denk
@ 2011-10-26 6:44 ` Eibach, Dirk
2011-10-28 6:25 ` Stefan Roese
0 siblings, 1 reply; 19+ messages in thread
From: Eibach, Dirk @ 2011-10-26 6:44 UTC (permalink / raw)
To: u-boot
Dear Wolfgang,
> In message <1319101940-780-1-git-send-email-eibach@gdsys.de>
> you wrote:
> > Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> > ---
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/pca9698.c | 143
> ++++++++++++++++++++++++++++++++++++++++++++++++
> > include/pca9698.h | 34 +++++++++++
> > 3 files changed, 178 insertions(+), 0 deletions(-) create mode
> > 100644 drivers/gpio/pca9698.c create mode 100644 include/pca9698.h
>
> is this some v3 of the patch? If so, where is the change
> log? What has been changes?
As you can see in http://patchwork.ozlabs.org/patch/120771/ message
archive I did a send without v3 tag and changelog by mistake.
The latest version with tag and changelog is
http://patchwork.ozlabs.org/patch/120777/.
Cheers
Dirk
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-26 6:44 ` Eibach, Dirk
@ 2011-10-28 6:25 ` Stefan Roese
2011-10-28 20:14 ` Wolfgang Denk
0 siblings, 1 reply; 19+ messages in thread
From: Stefan Roese @ 2011-10-28 6:25 UTC (permalink / raw)
To: u-boot
Hi Dirk,
On Wednesday 26 October 2011 08:44:56 Eibach, Dirk wrote:
> > is this some v3 of the patch? If so, where is the change
> > log? What has been changes?
>
> As you can see in http://patchwork.ozlabs.org/patch/120771/ message
> archive I did a send without v3 tag and changelog by mistake.
> The latest version with tag and changelog is
> http://patchwork.ozlabs.org/patch/120777/.
Perhaps its easiest if you could send an incremental patch, to bring the
upstream source to the latest one. As your new PPC4xx board support depends on
the new API.
Otherwise Wolfgang would need to revert the patch
486cad03be46114d726df56721ee27cba52c38e3 and apply the new one.
Wolfgang, what would you prefer? Should Dirk just send an incremental patch?
Best regards,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port
2011-10-28 6:25 ` Stefan Roese
@ 2011-10-28 20:14 ` Wolfgang Denk
0 siblings, 0 replies; 19+ messages in thread
From: Wolfgang Denk @ 2011-10-28 20:14 UTC (permalink / raw)
To: u-boot
Dear Stefan Roese,
In message <201110280825.08189.sr@denx.de> you wrote:
>
> Wolfgang, what would you prefer? Should Dirk just send an incremental patch?
Yes, please.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is more rational to sacrifice one life than six.
-- Spock, "The Galileo Seven", stardate 2822.3
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2011-10-28 20:14 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-10-04 9:13 [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port eibach at gdsys.de
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Do not stop booting on any keypress on intip eibach at gdsys.de
2011-10-12 9:49 ` Stefan Roese
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Improve lm63 pwm on dlvision-10g eibach at gdsys.de
2011-10-12 9:50 ` Stefan Roese
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Add Io64 board support eibach at gdsys.de
2011-10-06 21:09 ` Wolfgang Denk
2011-10-06 21:10 ` Wolfgang Denk
2011-10-04 9:13 ` [U-Boot] [PATCH] ppc4xx: Change DDR2 CL from 4 to 5 for intip eibach at gdsys.de
2011-10-12 9:50 ` Stefan Roese
2011-10-18 14:23 ` [U-Boot] [PATCH] gpio: Add PCA9698 40-bit I2C I/O port Stefan Roese
2011-10-21 22:43 ` Wolfgang Denk
-- strict thread matches above, loose matches on Subject: below --
2011-10-20 9:12 Dirk Eibach
2011-10-20 9:31 ` Stefan Roese
2011-10-20 9:40 ` Eibach, Dirk
2011-10-23 19:01 ` Wolfgang Denk
2011-10-26 6:44 ` Eibach, Dirk
2011-10-28 6:25 ` Stefan Roese
2011-10-28 20:14 ` Wolfgang Denk
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