[U-Boot] [PATCH 0/3] mpc85xx: HWW-1U-1A board support patches

[U-Boot] [PATCH 0/3] mpc85xx: HWW-1U-1A board support patches

[Kyle Moffett]

Hello,

This patch series is a resubmission of a series from several months
back.  It adds support for the eXMeritus HWW-1U-1A hardware.

I believe all of the prior review comments have been addressed.
This code is checkpatch clean using scripts/checkpatch.pl from the
Linux kernel GIT clone I did a few days ago.

Comments, critiques, and compliments are highly appreciated.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 1/3] mpc85xx: Add inline GPIO acessor functions

[Kyle Moffett]

To ease the implementation of other MPC85xx board ports, several common
GPIO helpers are added to <asm/mpc85xx_gpio.h>.

Since each of these compiles to no more than 4-5 instructions it would
be very inefficient to call them out of line, therefore we put them
entirely in the header file.

The HWW-1U-1A board port which these were written for strongly prefers
to set multiple GPIOs as a single batch operation, so the API is
designed around that basis.

To assist other board ports, a small set of wrappers are used which
provides a standard gpio_request() interface around the MPC85xx-specific
functions.  This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>

--

Changelog:
v2: Moved the inline functions to a non-board-specific header
v3: Added generic Linux-standard GPIO wrappers
v4: Improved comments and fixed minor bugs in the wrapper functions
v5: No changes
v6: Rebased onto the 'next' branch of git://git.denx.de/u-boot-mpc85xx.git
v7: No changes
v8: Rebased onto latest HEAD and add README entry for the config option
---
 README                                  |    5 ++
 arch/powerpc/include/asm/mpc85xx_gpio.h |  120 +++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpc85xx_gpio.h

diff --git a/README b/README
index 7e032a9..91412f2 100644
--- a/README
+++ b/README
@@ -359,6 +359,11 @@ The following options need to be configured:
 		ICache only when Code runs from RAM.
 
 - 85xx CPU Options:
+		CONFIG_MPC85XX_GENERIC_GPIO
+
+		Provide a generic gpio_request() interface to the onboard
+		processor GPIOs in the MPC85XX-series chips.
+
 		CONFIG_SYS_FSL_TBCLK_DIV
 
 		Defines the core time base clock divider ratio compared to the
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
new file mode 100644
index 0000000..ad54b4e
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/immap_85xx.h>
+
+/*
+ * The following internal functions are an MPC85XX-specific GPIO API which
+ * allows setting and querying multiple GPIOs in a single operation.
+ *
+ * All of these look relatively large, but the arguments are almost always
+ * constants, so they compile down to just a few instructions and a
+ * memory-mapped IO operation or two.
+ */
+static inline void mpc85xx_gpio_set(unsigned int mask,
+		unsigned int dir, unsigned int val)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+
+	/* First mask off the unwanted parts of "dir" and "val" */
+	dir &= mask;
+	val &= mask;
+
+	/* Now read in the values we're supposed to preserve */
+	dir |= (in_be32(&gpio->gpdir) & ~mask);
+	val |= (in_be32(&gpio->gpdat) & ~mask);
+
+	/*
+	 * Poke the new output values first, then set the direction.  This
+	 * helps to avoid transient data when switching from input to output
+	 * and vice versa.
+	 */
+	out_be32(&gpio->gpdat, val);
+	out_be32(&gpio->gpdir, dir);
+}
+
+static inline void mpc85xx_gpio_set_in(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0x00000000, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_low(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_high(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF);
+}
+
+static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+
+	/* Read the requested values */
+	return in_be32(&gpio->gpdat) & mask;
+}
+
+/*
+ * These implement the generic Linux GPIO API on top of the other functions
+ * in this header.
+ */
+#ifdef CONFIG_MPC85XX_GENERIC_GPIO
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+	/* Compatibility shim */
+	return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+	/* Compatibility shim */
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+	mpc85xx_gpio_set_in(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+	mpc85xx_gpio_set_low(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+	return !!mpc85xx_gpio_get(1U << gpio)
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
+}
+
+static inline int gpio_is_valid(int gpio)
+{
+	return (gpio >= 0) && (gpio < 32);
+}
+#endif /* CONFIG_MPC85XX_GENERIC_GPIO */
-- 
1.7.2.5

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Kyle Moffett]

The HWW-1U-1A board needs to be able to override the "reset" command due
to hardware design limitations.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>

--

Changelog:
v2: Removed in favor of more involved reset rework
v6: Resurrected again (the more involved rework was NAKed)
v7: Fixed remaining checkpatch errors
v8: Also hook __board_restart() from the pre-PQ3 do_reset() code.
    Rebased onto the latest HEAD.
---
 arch/powerpc/cpu/mpc85xx/cpu.c |   32 +++++++++++++++++++++++++++-----
 1 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 49c0551..81a17bc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -195,13 +195,24 @@ int checkcpu (void)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+/* Board-specific reset stub */
+__attribute__((__weak__))
+int __board_restart(void)
 {
-/* Everything after the first generation of PQ3 parts has RSTCR */
+	return 0;
+}
+
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
     defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
 	unsigned long val, msr;
 
+	/* Allow boards to override the reset */
+	int err = __board_restart();
+	if (err)
+		return err;
+
 	/*
 	 * Initiate hard reset in debug control register DBCR0
 	 * Make sure MSR[DE] = 1.  This only resets the core.
@@ -213,14 +224,25 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	val = mfspr(DBCR0);
 	val |= 0x70000000;
 	mtspr(DBCR0,val);
+}
 #else
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* Everything after the first generation of PQ3 parts has RSTCR */
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* Allow boards to override the reset */
+	int err = __board_restart();
+	if (err)
+		return err;
+
 	out_be32(&gur->rstcr, 0x2);	/* HRESET_REQ */
 	udelay(100);
-#endif
-
 	return 1;
 }
+#endif
+
+
 
 
 /*
-- 
1.7.2.5

[U-Boot] [PATCH 3/3] mpc85xx: Add board support for the eXMeritus HWW-1U-1A devices

[Kyle Moffett]

The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones.  Two independent P2020 computers may
be found inside each zone.  Complete hardware support is included.

High-level hardware overview:
  * DO-160 certified for passenger aircraft (noncritical)
  * TEMPEST ceritified for RED/BLACK separation
  * 3 zones per chassis, 2 computers per zone (total of 6)
  * Dual-core 1.066GHz P2020 per computer
  * One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
  * Removable 80GB or 160GB Intel X18-M SSD per computer
  * Front-accessible dual-port E1000E per computer
  * Front-accessible serial console per computer
  * Front-accessible USB port per computer
  * Internal Gigabit crossover within each TEMPEST zone
  * Internal unidirectional fiber links across TEMPEST zones
  * Battery-backed DS1339 I2C RTC on each CPU.

Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.

Additional notes:
  * SPD detection is only known to work with the DO-160-certified DIMMs

  * A U-Boot built with 36-bit address-space seems to work, but I don't
    yet have a usable 36-bit kernel or DTB, so it's mostly untested.

  * CPU reset is a little quirky due to hardware misfeature, see the
    extensive comments in the board_reset() function in hww1u1a.c

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
---
 MAINTAINERS                       |    4 +
 board/exmeritus/hww1u1a/Makefile  |   48 ++++
 board/exmeritus/hww1u1a/ddr.c     |   34 +++
 board/exmeritus/hww1u1a/gpios.h   |   69 +++++
 board/exmeritus/hww1u1a/hww1u1a.c |  549 +++++++++++++++++++++++++++++++++++++
 board/exmeritus/hww1u1a/law.c     |   34 +++
 board/exmeritus/hww1u1a/tlb.c     |  106 +++++++
 boards.cfg                        |    2 +
 include/configs/HWW1U1A.h         |  473 ++++++++++++++++++++++++++++++++
 9 files changed, 1319 insertions(+), 0 deletions(-)
 create mode 100644 board/exmeritus/hww1u1a/Makefile
 create mode 100644 board/exmeritus/hww1u1a/ddr.c
 create mode 100644 board/exmeritus/hww1u1a/gpios.h
 create mode 100644 board/exmeritus/hww1u1a/hww1u1a.c
 create mode 100644 board/exmeritus/hww1u1a/law.c
 create mode 100644 board/exmeritus/hww1u1a/tlb.c
 create mode 100644 include/configs/HWW1U1A.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bb95e6d..9de41f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -319,6 +319,10 @@ Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 	TOP5200		MPC5200
 	TOP9000		ARM926EJS (AT91SAM9xxx SoC)
 
+Kyle Moffett <Kyle.D.Moffett@boeing.com>
+
+	HWW1U1A		P2020
+
 Tolunay Orkun <torkun@nextio.com>
 
 	csb272		PPC405GP
diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile
new file mode 100644
index 0000000..808d047
--- /dev/null
+++ b/board/exmeritus/hww1u1a/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_DDR_SPD) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
new file mode 100644
index 0000000..36d02ad
--- /dev/null
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * We only support one DIMM, so according to the P2020 docs we should
+	 * set the options as follows:
+	 */
+	popts->cs_local_opts[0].odt_rd_cfg = 0;
+	popts->cs_local_opts[0].odt_wr_cfg = 4;
+	popts->cs_local_opts[1].odt_rd_cfg = 0;
+	popts->cs_local_opts[1].odt_wr_cfg = 0;
+	popts->half_strength_driver_enable = 0;
+
+	/* Manually configured for our static clock rate */
+	popts->clk_adjust = 4;
+	popts->cpo_override = 4;
+	popts->write_data_delay = 2;
+	popts->twoT_en = 0;
+}
diff --git a/board/exmeritus/hww1u1a/gpios.h b/board/exmeritus/hww1u1a/gpios.h
new file mode 100644
index 0000000..ac56d42
--- /dev/null
+++ b/board/exmeritus/hww1u1a/gpios.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/mpc85xx_gpio.h>
+
+/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
+#define GPIO_CPU_ID		(1UL << (31 -  8))
+#define GPIO_BLUE_LED		(1UL << (31 -  9))
+#define GPIO_DIMM_RESET		(1UL << (31 - 10))
+#define GPIO_USB_RESET		(1UL << (31 - 11))
+#define GPIO_UNUSED_12		(1UL << (31 - 12))
+#define GPIO_GETH0_RESET	(1UL << (31 - 13))
+#define GPIO_RS422_RE		(1UL << (31 - 14))
+#define GPIO_RS422_DE		(1UL << (31 - 15))
+#define IRQ_I2CINT		(1UL << (31 - 20))
+#define IRQ_FANINT		(1UL << (31 - 21))
+#define IRQ_DIMM_EVENT		(1UL << (31 - 22))
+
+#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
+
+/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
+#define GPIO_CPUA_UNUSED_0	(1UL << (31 -  0))
+#define GPIO_CPUA_CPU_READY	(1UL << (31 -  1))
+#define GPIO_CPUA_DEBUG_LED2	(1UL << (31 -  2))
+#define GPIO_CPUA_DEBUG_LED1	(1UL << (31 -  3))
+#define GPIO_CPUA_TDIS2B	(1UL << (31 -  4)) /* MAC 2 TX B */
+#define GPIO_CPUA_TDIS2A	(1UL << (31 -  5)) /* MAC 2 TX A */
+#define GPIO_CPUA_TDIS1B	(1UL << (31 -  6)) /* MAC 1 TX B */
+#define GPIO_CPUA_TDIS1A	(1UL << (31 -  7)) /* MAC 1 TX A */
+#define IRQ_CPUA_UNUSED_0	(1UL << (31 - 16))
+#define IRQ_CPUA_UNUSED_1	(1UL << (31 - 17))
+#define IRQ_CPUA_UNUSED_2	(1UL << (31 - 18))
+#define IRQ_CPUA_UNUSED_3	(1UL << (31 - 19))
+
+/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
+#define GPIO_CPUB_RMUX_SEL1B	(1UL << (31 -  0))
+#define GPIO_CPUB_RMUX_SEL0B	(1UL << (31 -  1))
+#define GPIO_CPUB_RMUX_SEL1A	(1UL << (31 -  2))
+#define GPIO_CPUB_RMUX_SEL0A	(1UL << (31 -  3))
+#define GPIO_CPUB_UNUSED_4	(1UL << (31 -  4))
+#define GPIO_CPUB_CPU_READY	(1UL << (31 -  5))
+#define GPIO_CPUB_DEBUG_LED2	(1UL << (31 -  6))
+#define GPIO_CPUB_DEBUG_LED1	(1UL << (31 -  7))
+#define IRQ_CPUB_SD_1A		(1UL << (31 - 16))
+#define IRQ_CPUB_SD_2B		(1UL << (31 - 17))
+#define IRQ_CPUB_SD_2A		(1UL << (31 - 18))
+#define IRQ_CPUB_SD_1B		(1UL << (31 - 19))
+
+/* If it isn't CPU A then it's CPU B */
+static inline unsigned int hww1u1a_is_cpu_a(void)
+{
+	return !mpc85xx_gpio_get(GPIO_CPU_ID);
+}
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
new file mode 100644
index 0000000..f79f5b5
--- /dev/null
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -0,0 +1,549 @@
+/*
+ * Copyright 2009-2011 eXMeritus, A Boeing Company
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <linux/ctype.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+#include "gpios.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	unsigned int gpio_high = 0;
+	unsigned int gpio_low  = 0;
+	unsigned int gpio_in   = 0;
+	unsigned int i;
+
+	puts("Board: HWW-1U-1A ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+
+	/*
+	 * First just figure out which CPU we're on, then use that to
+	 * configure the lists of other GPIOs to be programmed.
+	 */
+	mpc85xx_gpio_set_in(GPIO_CPU_ID);
+	if (hww1u1a_is_cpu_a()) {
+		puts("CPU A\n");
+
+		/* We want to turn on some LEDs */
+		gpio_high |= GPIO_CPUA_CPU_READY;
+		gpio_low  |= GPIO_CPUA_DEBUG_LED1;
+		gpio_low  |= GPIO_CPUA_DEBUG_LED2;
+
+		/* Disable the unused transmitters */
+		gpio_low  |= GPIO_CPUA_TDIS1A;
+		gpio_high |= GPIO_CPUA_TDIS1B;
+		gpio_low  |= GPIO_CPUA_TDIS2A;
+		gpio_high |= GPIO_CPUA_TDIS2B;
+	} else {
+		puts("CPU B\n");
+
+		/* We want to turn on some LEDs */
+		gpio_high |= GPIO_CPUB_CPU_READY;
+		gpio_low  |= GPIO_CPUB_DEBUG_LED1;
+		gpio_low  |= GPIO_CPUB_DEBUG_LED2;
+
+		/* Enable the appropriate receivers */
+		gpio_high |= GPIO_CPUB_RMUX_SEL0A;
+		gpio_high |= GPIO_CPUB_RMUX_SEL0B;
+		gpio_low  |= GPIO_CPUB_RMUX_SEL1A;
+		gpio_low  |= GPIO_CPUB_RMUX_SEL1B;
+	}
+
+	/* These GPIOs are common */
+	gpio_in   |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
+	gpio_low  |= GPIO_RS422_RE;
+	gpio_high |= GPIO_RS422_DE;
+
+	/* Ok, now go ahead and program all of those in one go */
+	mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
+			 gpio_high|gpio_low,
+			 gpio_high);
+
+	/*
+	 * If things have been taken out of reset early (for example, by one
+	 * of the BDI3000 debuggers), then we need to put them back in reset
+	 * and delay a while before we continue.
+	 */
+	if (mpc85xx_gpio_get(GPIO_RESETS)) {
+		ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+		puts("Debugger detected... extra device reset enabled!\n");
+
+		/* Put stuff into reset and disable the DDR controller */
+		mpc85xx_gpio_set_low(GPIO_RESETS);
+		out_be32(&ddr->sdram_cfg, 0x00000000);
+
+		puts("    Waiting 1 sec for reset...");
+		for (i = 0; i < 10; i++) {
+			udelay(100000);
+			puts(".");
+		}
+		puts("\n");
+	}
+
+	/* Now bring everything back out of reset again */
+	mpc85xx_gpio_set_high(GPIO_RESETS);
+	return 0;
+}
+
+/*
+ * This little shell function just returns whether or not it's CPU A.
+ * It can be used to select the right device-tree when booting, etc.
+ */
+int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (argc > 1)
+		cmd_usage(cmdtp);
+
+	if (hww1u1a_is_cpu_a())
+		return 0;
+	else
+		return 1;
+}
+U_BOOT_CMD(
+	hww1u1a_test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
+	"Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
+	" && <command-if-true>\n"
+	"hww1u1a_test_cpu_a || <command-if-false>\n"
+);
+
+/* Create a prompt-like string: "uboot at HOSTNAME% " */
+#define PROMPT_PREFIX "uboot at exm"
+#define PROMPT_SUFFIX "% "
+
+/* This function returns a PS1 prompt based on the serial number */
+static char *hww1u1a_prompt;
+const char *hww1u1a_get_ps1(void)
+{
+	unsigned long len, i, j;
+	const char *serialnr;
+
+	/* If our prompt was already set, just use that */
+	if (hww1u1a_prompt)
+		return hww1u1a_prompt;
+
+	/* Use our serial number if present, otherwise a default */
+	serialnr = getenv("serial#");
+	if (!serialnr || !serialnr[0])
+		serialnr = "999999-X";
+
+	/*
+	 * We will turn the serial number into a hostname by:
+	 *   (A) Delete all non-alphanumerics.
+	 *   (B) Lowercase all letters.
+	 *   (C) Prefix "exm".
+	 *   (D) Suffix "a" for CPU A and "b" for CPU B.
+	 */
+	for (i = 0, len = 0; serialnr[i]; i++) {
+		if (isalnum(serialnr[i]))
+			len++;
+	}
+
+	len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
+	hww1u1a_prompt = malloc(len);
+	if (!hww1u1a_prompt)
+		return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
+
+	/* Now actually fill it in */
+	i = 0;
+
+	/* Handle the prefix */
+	for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
+		hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
+
+	/* Now the serial# part of the hostname */
+	for (j = 0; serialnr[j]; j++)
+		if (isalnum(serialnr[j]))
+			hww1u1a_prompt[i++] = tolower(serialnr[j]);
+
+	/* Now the CPU id ("a" or "b") */
+	hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
+
+	/* Finally the suffix */
+	for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
+		hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
+
+	/* This should all have added up, but just in case */
+	hww1u1a_prompt[len - 1] = '\0';
+
+	/* Now we're done */
+	return hww1u1a_prompt;
+}
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap bootflash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for FLASH */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	struct fsl_pq_mdio_info mdio_info;
+
+	SET_STD_TSEC_INFO(tsec_info[0], 1);
+	SET_STD_TSEC_INFO(tsec_info[1], 2);
+	SET_STD_TSEC_INFO(tsec_info[2], 3);
+
+	if (hww1u1a_is_cpu_a())
+		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
+	else
+		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, 3);
+	return pci_eth_init(bis);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+}
+
+/*
+ * Unfortunately we have a bit of a problem with our reset line wiring on the
+ * HWW-1U-1A boards.
+ *
+ * Specifically the "CPU A" reset controls all of the PCI devices on the
+ * IO/backplane card, which means ethernet and SATA controllers for both
+ * CPU A *and* CPU B.
+ *
+ * This is somewhat of a problem if the CPUs are reset independently... CPU B
+ * might fail to come up because his PCI devices are confused, or CPU B might
+ * die because CPU A just reset the SATA controller for his root filesystem.
+ *
+ * Since in practice the CPUs never need to reboot independently we will go
+ * ahead and require GPIO cross-communication between them before either one
+ * will reset.
+ *
+ * The communication protocol uses GPIOs 4-7 on the PCA9554 GPIO expander
+ * found on I2C-2@address 0x3f.  CPU A uses 4,5 as TX and 6,7 as RX; for
+ * CPU B we use the exact opposite.
+ *
+ * The GPIOs initialize as inputs during poweron, and are pulled high; the
+ * PCA9554 expanders will maintain valid outputs over soft-reset allowing for
+ * reliable operation.
+ *
+ * To avoid duplication, we will assign names to the GPIOs:
+ *            ,---------------------------------------.
+ *            |  GPIO4  |  GPIO5  |  GPIO6  |  GPIO7  |
+ *  ,---------|=========|=========|=========|=========|
+ *  |  CPU A  |   tx1   |   tx2   |   rx1   |   rx2   |
+ *  |---------|---------|---------|---------|---------|
+ *  |  CPU B  |   rx1   |   rx2   |   tx1   |   tx2   |
+ *  `-------------------------------------------------'
+ *
+ * The state machine for each CPU is below.  In simplistic terms, each CPU
+ * waits until the other has cleared its GPIOs, then cause a tx1 high=>low
+ * transition.  Upon seeing the other CPU do the same, it will perform a
+ * tx2 high=>low transition and again wait.
+ *
+ * Once both CPUs have performed and seen both transitions, they will each
+ * set tx1 high (to create an "invalid" state) and then reset.
+ *
+ *       ,--------------.
+ *       | START/ERROR: |<==-.
+ *  ,-==>|   tx2 = 1;   |   || (rx2 == 0)
+ *  ||   |   tx1 = 1;   | ==-'
+ *  ||   `--------------'
+ *  ||          ||
+ *  ||          ||  (rx2 == 1)
+ *  ||          \/
+ *  ||   ,--------------.
+ *  ||   | WAITING:     |<==-.
+ *  |\== |   tx1 = 0;   |   || (rx1 == 1) && (rx2 == 1)
+ *  ||   |              | ==-'
+ *  ||   `--------------'
+ *  ||          ||
+ *  ||          ||  (rx1 == 0) && (rx2 == 1)
+ *  ||          \/
+ *  ||   ,--------------.
+ *  ||   | BOTH_READY:  |<==-.
+ *  `-== |   tx2 = 0;   |   || (rx1 == 0) && (rx2 == 1)
+ *       |              | ==-'
+ *       `--------------'
+ *              ||
+ *              ||  (rx2 == 0)
+ *              \/
+ *       ,--------------.
+ *       | RESETTING:   |
+ *       |   tx1 = 1;   |
+ *       |   reset();   |
+ *       `--------------'
+ *
+ * While in the "BOTH_READY" state a high-to-low rx2 transition must be
+ * followed within 50ms by activation of the HRESET_REQ signal.  That
+ * state MUST NOT be interrupted by any event other than the observed
+ * event (rx1 == high) && (rx2 == high).
+ */
+
+/*
+ * These tiny wrappers hardcode the I2C bus and the chip address to make the
+ * state-machine function easier to read and understand.
+ */
+#define PCA9554 CONFIG_SYS_I2C_PCA953X_ADDR
+static int pca9554_set_low(u8 gpio)
+{
+	i2c_set_bus_num(1);
+	return pca953x_set_val(PCA9554, (1U << gpio), 0x00);
+}
+
+static int pca9554_set_high(u8 gpio)
+{
+	i2c_set_bus_num(1);
+	return pca953x_set_val(PCA9554, (1U << gpio), 0xff);
+}
+
+static int pca9554_set_output(u8 gpio)
+{
+	i2c_set_bus_num(1);
+	return pca953x_set_dir(PCA9554, (1U << gpio), 0x00);
+}
+
+static int pca9554_set_input(u8 gpio)
+{
+	i2c_set_bus_num(1);
+	return pca953x_set_dir(PCA9554, (1U << gpio), 0xff);
+}
+
+int __board_restart(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 tx1, tx2, rx1, rx2, rxmask;
+	int ret;
+
+	/* Our state-machine state */
+	enum {
+		START_ERROR = 0,
+		WAITING,
+		BOTH_READY,
+	} state;
+
+	/* Check what CPU we are and configure accordingly. */
+	if (hww1u1a_is_cpu_a()) {
+		tx1 = 4; tx2 = 5; rx1 = 6; rx2 = 7;
+	} else {
+		rx1 = 4; rx2 = 5; tx1 = 6; tx2 = 7;
+	}
+	rxmask = (1U << rx1) | (1U << rx2);
+
+	printf("RESET: Preparing...");
+
+	/* First clear the "INVERT" setting on all relevant GPIOs */
+	i2c_set_bus_num(1);
+	if (pca953x_set_pol(PCA9554, 0xf0, 0x00) < 0)
+		goto err;
+
+	/* Configure both inputs */
+	if (pca9554_set_input(rx1) < 0)
+		goto err;
+	if (pca9554_set_input(rx2) < 0)
+		goto err;
+
+	/* Make sure the very first thing we do is set the "tx2" GPIO high */
+	if (pca9554_set_high(tx2) < 0)
+		goto err;
+	if (pca9554_set_output(tx2) < 0)
+		goto err;
+
+	/* Now reset our other transmit pin */
+	if (pca9554_set_high(tx1) < 0)
+		goto err;
+	if (pca9554_set_output(tx1) < 0)
+		goto err;
+
+	/* Enter the state machine */
+	state = START_ERROR;
+
+poll_state:
+	i2c_set_bus_num(1);
+	ret = pca953x_get_val(PCA9554);
+	switch (state) {
+	case START_ERROR:
+		if (ctrlc())
+			goto intr;
+
+		if (ret < 0)
+			goto err;
+
+		/* Wait for (rx2 == high) */
+		if (ret & (1U << rx2)) {
+			/* Success! */
+			state = WAITING;
+			goto enter_state;
+		}
+
+		goto poll_state;
+
+	case WAITING:
+		if (ctrlc())
+			goto intr;
+
+		if (ret < 0)
+			goto err;
+
+		/* Wait for (rx1 == low) && (rx2 == high) */
+		ret &= rxmask;
+		if (ret == (1U << rx2)) {
+			/* Success! */
+			state = BOTH_READY;
+			goto enter_state;
+		}
+		if (ret != rxmask) {
+			/* Oops, error */
+			state = START_ERROR;
+			goto enter_state;
+		}
+
+		goto poll_state;
+
+	case BOTH_READY:
+		/*
+		 * Non-interruptable wait for (rx2 == low), however if we
+		 * see (rx1 == high) and (rx2 == high) we should go back
+		 * to START_ERROR.
+		 */
+		if (ret < 0)
+			goto poll_state;
+
+		ret &= rxmask;
+		if (ret == rxmask) {
+			/* Oops, error */
+			state = START_ERROR;
+			goto enter_state;
+		}
+		if (ret & (1U << rx2))
+			goto poll_state;
+
+		/* Success, we have to reset quick now! */
+		(void)pca9554_set_high(tx1);
+
+		/* Turn on the "HRESET_REQ" pin (hard-reset request) */
+		printf("\nRESET: Hardware reset triggered, waiting...\n");
+		out_be32(&gur->rstcr, 0x2);
+		while (1)
+			udelay(10000);
+	}
+
+enter_state:
+	switch (state) {
+	case START_ERROR:
+		printf("\nRESET: Negotiation restart...");
+		/* Clear both GPIOs high in the right order */
+		if (pca9554_set_high(tx2) < 0)
+			goto err;
+		if (pca9554_set_high(tx1) < 0)
+			goto err;
+		if (ctrlc())
+			goto intr;
+
+		goto poll_state;
+
+	case WAITING:
+		printf("\nRESET: Waiting for peer...");
+		/* Set tx1 low */
+		if (pca9554_set_low(tx1) < 0)
+			goto err;
+		if (ctrlc())
+			goto intr;
+
+		goto poll_state;
+
+	case BOTH_READY:
+		printf("\nRESET: Both ready, point of no return...");
+		/* Point of no return: set tx2 low */
+		if (pca9554_set_low(tx2) < 0)
+			goto err;
+
+		goto poll_state;
+	}
+
+	/* We only get here through gotos */
+err:
+	printf("\nRESET: I2C communication error!\n");
+intr:
+	printf("\nRESET: Aborted!\n");
+	(void)pca9554_set_high(tx1);
+	(void)pca9554_set_high(tx2);
+	return -1;
+}
diff --git a/board/exmeritus/hww1u1a/law.c b/board/exmeritus/hww1u1a/law.c
new file mode 100644
index 0000000..1281c56
--- /dev/null
+++ b/board/exmeritus/hww1u1a/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c
new file mode 100644
index 0000000..6c65206
--- /dev/null
+++ b/board/exmeritus/hww1u1a/tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Boot page */
+	SET_TLB_ENTRY(1,	CONFIG_BPTR_VIRT_ADDR,
+				CONFIG_BPTR_VIRT_ADDR,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_CCSRBAR,
+				CONFIG_SYS_CCSRBAR_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * W**G* - FLASH (Will be *I*G* after relocation to RAM)
+	 *
+	 * This maps both SPI FLASH chips (128MByte per chip)
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_FLASH_BASE,
+				CONFIG_SYS_FLASH_BASE_PHYS,
+				MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+				0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI memory
+	 *
+	 * We have 1.5GB total PCI-E memory space to map and we want to use
+	 * the minimum possible number of TLB entries.  Since Book-E TLB
+	 * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT,
+				CONFIG_SYS_PCIE3_MEM_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 3, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 4, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI I/O
+	 *
+	 * This one entry covers all 3 64k PCI-E I/O windows
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_IO_VIRT,
+				CONFIG_SYS_PCIE3_IO_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 6, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index bd70a66..e1c16e7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -552,6 +552,8 @@ sbc8560                      powerpc     mpc85xx     sbc8560             -
 sbc8560_33                   powerpc     mpc85xx     sbc8560             -              -           sbc8560
 sbc8560_66                   powerpc     mpc85xx     sbc8560             -              -           sbc8560
 socrates                     powerpc     mpc85xx     socrates
+HWW1U1A                      powerpc     mpc85xx     hww1u1a             exmeritus
+HWW1U1A_36BIT                powerpc     mpc85xx     hww1u1a             exmeritus      -           HWW1U1A:36BIT
 MPC8536DS                    powerpc     mpc85xx     mpc8536ds           freescale      -           MPC8536DS
 MPC8536DS_36BIT              powerpc     mpc85xx     mpc8536ds           freescale      -           MPC8536DS:36BIT
 MPC8536DS_NAND               powerpc     mpc85xx     mpc8536ds           freescale      -           MPC8536DS:NAND
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
new file mode 100644
index 0000000..dad85ac
--- /dev/null
+++ b/include/configs/HWW1U1A.h
@@ -0,0 +1,473 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * HardwareWall HWW-1U-1A airborne unit configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High-level system configuration options */
+#define CONFIG_BOOKE		/* Power/PowerPC Book-E			*/
+#define CONFIG_E500		/* e500 (Power ISA v2.03 with SPE)	*/
+#define CONFIG_MPC85xx		/* MPC8540/60/55/41/48 family		*/
+#define CONFIG_FSL_ELBC		/* FreeScale Enhanced LocalBus Cntlr	*/
+#define CONFIG_FSL_LAW		/* FreeScale Local Access Window	*/
+#define CONFIG_P2020		/* FreeScale P2020			*/
+#define CONFIG_HWW1U1A		/* eXMeritus HardwareWall HWW-1U-1A	*/
+#define CONFIG_MP		/* Multiprocessing support		*/
+#define CONFIG_HWCONFIG		/* Use hwconfig from environment	*/
+
+#define CONFIG_L2_CACHE			/* L2 cache enabled		*/
+#define CONFIG_BTB			/* Branch predition enabled	*/
+
+#define CONFIG_PANIC_HANG		/* No board reset on panic	*/
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r()	*/
+#define CONFIG_CMD_REGINFO		/* Dump various CPU regs	*/
+
+/*
+ * Allow the use of 36-bit physical addresses in "HWW_1U_1A_36BIT" mode.
+ * NOTE: This is only very minimally tested and has known compatibility
+ * issues with the existing kernel images.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
+#endif
+
+/* Reserve plenty of RAM for malloc (we have 2GB+) */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* How much L2 cache do we map so we can use it as RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+/* This is our temporary global data area just above the stack */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/* The stack grows down from the global data area */
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Enable IRQs and watchdog with a 1000Hz system decrementer */
+#define CONFIG_CMD_IRQ
+#define CONFIG_SYS_HZ 1000
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * Clock crystal configuration:
+ *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
+ *  (2) CCB: Multiplier from SYS_CLK
+ *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
+ */
+#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
+#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
+ * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
+ * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
+ * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
+ * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
+ * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
+ * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
+ * 0xffe0_0000  0xffef_ffff    1M  CCSR
+ * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
+ */
+
+/* Virtual Memory Map */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+#define CONFIG_SYS_CCSRBAR		0xffe00000 /* CCSRBAR @ runtime */
+
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000 /* 64k */
+
+/* Physical Memory Map */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
+#define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
+#define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
+#define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
+#define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
+#define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
+#define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf		/* for ASM code */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000	/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf		/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000	/* for ASM code */
+#else
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0x80000000ul
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000ul
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000ul
+#define CONFIG_SYS_FLASH_BASE_PHYS     0xe0000000ul
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000ul
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000ul
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000ul
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS  0xffd00000ul
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0		/* for ASM code */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000	/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0x0		/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000	/* for ASM code */
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc /* Top address in flash */
+#define CONFIG_SYS_TEXT_BASE		0xeff80000 /* Start of U-Boot image */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x80000 /* 512kB (4 flash sectors) */
+
+/*
+ * U-Boot Environment Image:  The two sectors immediately below U-Boot
+ * form the U-Boot environment (regular and redundant).
+ */
+#define CONFIG_ENV_IS_IN_FLASH	/* The environment image is stored in FLASH */
+#define CONFIG_ENV_OVERWRITE	/* Allow "protected" variables to be erased */
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128kB (1 flash sector) */
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
+
+/* Only use 8kB of each environment sector for data */
+#define CONFIG_ENV_SIZE		0x2000 /* 8kB */
+#define CONFIG_ENV_SIZE_REDUND	0x2000 /* 8kB */
+
+
+/* -------------------------------------------------------------------- */
+
+/* Serial Console Configuration */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Echo back characters received during a serial download */
+#define CONFIG_LOADS_ECHO
+
+/* Allow a serial-download to temporarily change baud */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+
+/* -------------------------------------------------------------------- */
+
+/* PCI and PCI-Express Support */
+#define CONFIG_PCI		/* Enable PCI/PCIE			*/
+#define CONFIG_PCI_PNP		/* Scan PCI busses			*/
+#define CONFIG_CMD_PCI		/* Enable the "pci" command		*/
+#define CONFIG_FSL_PCI_INIT	/* Common FreeScale PCI initialization	*/
+#define CONFIG_FSL_PCIE_RESET	/* We have PCI-E reset errata		*/
+#define CONFIG_SYS_PCI_64BIT	/* PCI resources are 64-bit		*/
+#define CONFIG_PCI_SCAN_SHOW	/* Display PCI scan during boot		*/
+
+/* Enable 2 of the 3 PCI-E controllers */
+#define CONFIG_PCIE3
+#undef  CONFIG_PCIE2
+#define CONFIG_PCIE1
+
+/* Display human-readable names when initializing */
+#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
+#define CONFIG_SYS_PCIE2_NAME "Unused"
+#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
+
+/*
+ * PCI bus addresses
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/* Generic FreeScale hardware I2C support */
+#define CONFIG_HARD_I2C
+#define CONFIG_FSL_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C bus configuration */
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+/* Turn off RTC square-wave output to save battery */
+#define CONFIG_SYS_RTC_DS1337_NOOSC
+
+/* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
+
+
+/* -------------------------------------------------------------------- */
+
+/* FreeScale DDR2/3 SDRAM Controller */
+#define CONFIG_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
+#define CONFIG_DDR_ECC		/* Enable ECC by default		*/
+#define CONFIG_DDR_SPD		/* Detect DDR config from SPD EEPROM	*/
+#define CONFIG_SPD_EEPROM	/* ...why 2 config variables for this?	*/
+#define CONFIG_VERY_BIG_RAM	/* Allow 2GB+ of RAM			*/
+#define CONFIG_CMD_SDRAM
+
+/* Standard P2020 DDR controller parameters */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* Make sure to tell the DDR controller to preinitialze all of RAM */
+#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+
+/* -------------------------------------------------------------------- */
+
+/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+/* Flash banks (2x 128MB) */
+#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
+#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
+
+/*
+ * Flash access modes and timings (values are the defaults after a RESET).
+ *
+ * NOTE: These could probably be optimized but are more than sufficient for
+ * this particular system for the moment.
+ */
+#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
+#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+		| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Configure both flash banks */
+#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
+#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
+#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
+#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
+
+/* Flash timeouts (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)	*/
+
+/* Quiet flash testing */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+/* Make program/erase count down from 45/5 (9....8....7....) */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+
+/* -------------------------------------------------------------------- */
+
+/* Ethernet Device Support */
+#define CONFIG_MII			/* Enable MII PHY code		*/
+#define CONFIG_MII_DEFAULT_TSEC		/* ??? Copied from P2020DS	*/
+#define CONFIG_PHY_GIGE			/* Support Gigabit PHYs		*/
+#define CONFIG_ETHPRIME "e1000#0"	/* Default to external ports	*/
+
+/* Turn on various helpful networking commands */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
+/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
+#define CONFIG_TSEC_ENET
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC3
+#define CONFIG_TSEC1_NAME "owt0"
+#define CONFIG_TSEC2_NAME "owt1"
+#define CONFIG_TSEC3_NAME "peer"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC1_PHY_ADDR      2
+#define TSEC2_PHY_ADDR      3
+#define TSEC3_PHY_ADDR      4
+#define TSEC3_PHY_ADDR_CPUA 4
+#define TSEC3_PHY_ADDR_CPUB 5
+
+/* PCI-E dual-port E1000 (external ethernet ports) */
+#define CONFIG_E1000
+#define CONFIG_E1000_SPI
+#define CONFIG_E1000_SPI_GENERIC
+#define CONFIG_CMD_E1000
+
+/* We need the SPI infrastructure to poke the E1000's EEPROM */
+#define CONFIG_SPI
+#define CONFIG_SPI_X
+#define CONFIG_CMD_SPI
+#define MAX_SPI_BYTES 32
+
+
+/* -------------------------------------------------------------------- */
+
+/* USB Thumbdrive Device Support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_USB
+
+/* Partition and Filesystem support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+
+/* -------------------------------------------------------------------- */
+
+/* Command line configuration. */
+#define CONFIG_CMDLINE_EDITING		/* Enable command editing	*/
+#define CONFIG_COMMAND_HISTORY		/* Enable command history	*/
+#define CONFIG_AUTO_COMPLETE		/* Enable command completion	*/
+#define CONFIG_SYS_LONGHELP		/* Enable detailed command help	*/
+#define CONFIG_SYS_MAXARGS 128		/* Up to 128 command-line args	*/
+#define CONFIG_SYS_PBSIZE 8192		/* Allow up to 8k printed lines	*/
+#define CONFIG_SYS_CBSIZE 4096		/* Allow up to 4k command lines	*/
+#define CONFIG_SYS_BARGSIZE 4096	/* Allow up to 4k boot args	*/
+#define CONFIG_SYS_HUSH_PARSER		/* Enable a fancier shell	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "	/* Command-line continuation	*/
+
+/* A little extra magic here for the prompt */
+#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
+#ifndef __ASSEMBLY__
+const char *hww1u1a_get_ps1(void);
+#endif
+
+/* Include a bunch of default commands we probably want */
+#include <config_cmd_default.h>
+
+/* Other helpful shell-like commands */
+#define CONFIG_MD5
+#define CONFIG_SHA1
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_SHA1
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SETEXPR
+
+
+/* -------------------------------------------------------------------- */
+
+/* Image manipulation and booting */
+
+/* We use the OpenFirmware-esque "Flattened Device Tree" */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)	/* Maximum kernel memory map	*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)	/* Maximum kernel size of 64MB	*/
+
+/* This is the default address for commands with an optional address arg */
+#define CONFIG_LOADADDR		  100000
+#define CONFIG_SYS_LOAD_ADDR	0x100000
+
+/* Test memory starting from the default load address to just below 2GB */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_END		0x7f000000
+
+#define CONFIG_BOOTDELAY 20
+#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
+#define CONFIG_BOOTARGS ""
+#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
+
+/* Extra environment parameters */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
+	"perf_mode=performance\0"					\
+	"hwconfig="	"fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"	\
+			"usb1:dr_mode=host,phy_type=ulpi\0"		\
+	"flkernel=0xe8020000\0"						\
+	"flinitramfs=0xe8800000\0"					\
+	"fldevicetree=0xeff20000\0"					\
+	"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"	\
+	"flboot=run preboot; run flbootm\0"
+
+#endif	/* __CONFIG_H */
-- 
1.7.2.5

[U-Boot] [PATCH 1/3] mpc85xx: Add inline GPIO acessor functions

[Mike Frysinger]

On Tuesday 18 October 2011 19:41:22 Kyle Moffett wrote:
> --- a/README
> +++ b/README
> 
>  - 85xx CPU Options:
> +		CONFIG_MPC85XX_GENERIC_GPIO
> +
> +		Provide a generic gpio_request() interface to the onboard
> +		processor GPIOs in the MPC85XX-series chips.

do you really need a CONFIG knob for this ?  defining this adds no overhead 
that i can see.

> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h

missing #ifdef protection against multiple inclusion
-mike
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[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Mike Frysinger]

On Tuesday 18 October 2011 19:41:23 Kyle Moffett wrote:
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
>  	unsigned long val, msr;
> 
> +	/* Allow boards to override the reset */
> +	int err = __board_restart();
> +	if (err)
> +		return err;

i thought we decided that do_reset() shouldn't return
-mike
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[U-Boot] [PATCH 1/3] mpc85xx: Add inline GPIO acessor functions

[Kumar Gala]

On Oct 18, 2011, at 10:19 PM, Mike Frysinger wrote:

> On Tuesday 18 October 2011 19:41:22 Kyle Moffett wrote:
>> --- a/README
>> +++ b/README
>> 
>> - 85xx CPU Options:
>> +		CONFIG_MPC85XX_GENERIC_GPIO
>> +
>> +		Provide a generic gpio_request() interface to the onboard
>> +		processor GPIOs in the MPC85XX-series chips.
> 
> do you really need a CONFIG knob for this ?  defining this adds no overhead 
> that i can see.

I agree, wasn't paying attention that this is just in a .h, so lets remove the CONFIG_ option bits (both in README and in .h)

>> --- /dev/null
>> +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
> 
> missing #ifdef protection against multiple inclusion

please fix.

- k

[U-Boot] [PATCH 1/3] mpc85xx: Add inline GPIO acessor functions

[Moffett, Kyle D]

On Oct 19, 2011, at 09:51, Kumar Gala wrote:
> On Oct 18, 2011, at 10:19 PM, Mike Frysinger wrote:
>> On Tuesday 18 October 2011 19:41:22 Kyle Moffett wrote:
>>> --- a/README
>>> +++ b/README
>>> 
>>> - 85xx CPU Options:
>>> +		CONFIG_MPC85XX_GENERIC_GPIO
>>> +
>>> +		Provide a generic gpio_request() interface to the onboard
>>> +		processor GPIOs in the MPC85XX-series chips.
>> 
>> do you really need a CONFIG knob for this ?  defining this adds no overhead 
>> that i can see.
> 
> I agree, wasn't paying attention that this is just in a .h, so lets remove the CONFIG_ option bits (both in README and in .h)

Well, I was concerned that this API could conflict with another provider
of the generic GPIO interface (IE: An I2C GPIO chip or whatever).

Looking further it appears that only 3-4 drivers implement the generic
GPIO interface, and all of those are CPU-specific, so it should not be a
problem in practice.

The reason I originally made this configurable was because I did not
want or need the generic GPIO interface; I needed an API that let me set
a large group of GPIOs simultaneously.  During an early review it was
asked why I didn't use the standard interface; so I implemented the
simple wrapper functions.

I've removed the CONFIG_* option and will be resubmitting that patch shortly.

>>> --- /dev/null
>>> +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
>> 
>> missing #ifdef protection against multiple inclusion
> 
> please fix.

Really?  Oops!  I have no idea how I missed that.  Fixed.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Moffett, Kyle D]

On Oct 18, 2011, at 23:20, Mike Frysinger wrote:
> On Tuesday 18 October 2011 19:41:23 Kyle Moffett wrote:
>> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> +{
>> 	unsigned long val, msr;
>> 
>> +	/* Allow boards to override the reset */
>> +	int err = __board_restart();
>> +	if (err)
>> +		return err;
> 
> i thought we decided that do_reset() shouldn't return
> -mike

For our hardware we have to coordinate reset between both CPUs on the
same physical board, so a "reset" command may hang indefinitely waiting
for the other CPU (IE: If it refuses to shutdown in Linux or is running
U-Boot).

So for user convenience I need to be able to Ctrl-C the communication.
Since "reset" is basically just like any other U-Boot shell command,
(except with some side-effects) it seems reasonable to allow a board
handler to return an error instead of resetting.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Mike Frysinger]

On Wednesday 19 October 2011 14:26:03 Moffett, Kyle D wrote:
> On Oct 18, 2011, at 23:20, Mike Frysinger wrote:
> > On Tuesday 18 October 2011 19:41:23 Kyle Moffett wrote:
> >> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> >> +{
> >> 
> >> 	unsigned long val, msr;
> >> 
> >> +	/* Allow boards to override the reset */
> >> +	int err = __board_restart();
> >> +	if (err)
> >> +		return err;
> > 
> > i thought we decided that do_reset() shouldn't return
> 
> For our hardware we have to coordinate reset between both CPUs on the
> same physical board, so a "reset" command may hang indefinitely waiting
> for the other CPU (IE: If it refuses to shutdown in Linux or is running
> U-Boot).
> 
> So for user convenience I need to be able to Ctrl-C the communication.
> Since "reset" is basically just like any other U-Boot shell command,
> (except with some side-effects) it seems reasonable to allow a board
> handler to return an error instead of resetting.

i thought this came up before and we said "no".  but Wolfgang was more 
involved in that discussion, so he should be able to better say.

this is probably in the mail archives somewhere too ...
-mike
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[U-Boot] [PATCH 2/3] mpc85xx: Add inline GPIO acessor functions

[Kyle Moffett]

To ease the implementation of other MPC85xx board ports, several common
GPIO helpers are added to <asm/mpc85xx_gpio.h>.

Since each of these compiles to no more than 4-5 instructions it would
be very inefficient to call them out of line, therefore we put them
entirely in the header file.

The HWW-1U-1A board port which these were written for strongly prefers
to set multiple GPIOs as a single batch operation, so the API is
designed around that basis.

To assist other board ports, a small set of wrappers are used which
provides a standard gpio_request() interface around the MPC85xx-specific
functions.  This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>

--

Changelog:
v2: Moved the inline functions to a non-board-specific header
v3: Added generic Linux-standard GPIO wrappers
v4: Improved comments and fixed minor bugs in the wrapper functions
v5: No changes
v6: Rebased onto the 'next' branch of git://git.denx.de/u-boot-mpc85xx.git
v7: No changes
v8: Rebased onto latest HEAD and add README entry for the config option
v9: Removed CONFIG_* option and added missing #ifdef protection
---
 arch/powerpc/include/asm/mpc85xx_gpio.h |  123 +++++++++++++++++++++++++++++++
 1 files changed, 123 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpc85xx_gpio.h

diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
new file mode 100644
index 0000000..bcf5b86
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef  POWERPC_ASM_MPC85XX_GPIO_H_
+# define POWERPC_ASM_MPC85XX_GPIO_H_ 1
+
+# include <asm/immap_85xx.h>
+
+/*
+ * The following internal functions are an MPC85XX-specific GPIO API which
+ * allows setting and querying multiple GPIOs in a single operation.
+ *
+ * All of these look relatively large, but the arguments are almost always
+ * constants, so they compile down to just a few instructions and a
+ * memory-mapped IO operation or two.
+ */
+static inline void mpc85xx_gpio_set(unsigned int mask,
+		unsigned int dir, unsigned int val)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+
+	/* First mask off the unwanted parts of "dir" and "val" */
+	dir &= mask;
+	val &= mask;
+
+	/* Now read in the values we're supposed to preserve */
+	dir |= (in_be32(&gpio->gpdir) & ~mask);
+	val |= (in_be32(&gpio->gpdat) & ~mask);
+
+	/*
+	 * Poke the new output values first, then set the direction.  This
+	 * helps to avoid transient data when switching from input to output
+	 * and vice versa.
+	 */
+	out_be32(&gpio->gpdat, val);
+	out_be32(&gpio->gpdir, dir);
+}
+
+static inline void mpc85xx_gpio_set_in(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0x00000000, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_low(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_high(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF);
+}
+
+static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+
+	/* Read the requested values */
+	return in_be32(&gpio->gpdat) & mask;
+}
+
+/*
+ * These implement the generic Linux GPIO API on top of the other functions
+ * in this header.
+ */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+	/* Compatibility shim */
+	return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+	/* Compatibility shim */
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+	mpc85xx_gpio_set_in(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+	mpc85xx_gpio_set_low(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+	return !!mpc85xx_gpio_get(1U << gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
+}
+
+static inline int gpio_is_valid(int gpio)
+{
+	return (gpio >= 0) && (gpio < 32);
+}
+
+#endif /* not POWERPC_ASM_MPC85XX_GPIO_H_ */
-- 
1.7.2.5

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Wolfgang Denk]

Dear Mike Frysinger,

In message <201110191452.26073.vapier@gentoo.org> you wrote:
>
> i thought this came up before and we said "no".  but Wolfgang was more 
> involved in that discussion, so he should be able to better say.

Yes, we said no.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I'm what passes for a Unix guru in my office. This is  a  frightening
concept. - Lee Ann Goldstein, in <3k55ba$c43@butch.lmsc.lockheed.com>

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Wolfgang Denk]

Dear "Moffett, Kyle D",

In message <7C2673D7-CC5C-490C-9809-06C9A207154F@boeing.com> you wrote:
>
> Since "reset" is basically just like any other U-Boot shell command,

No, it ain't.

> (except with some side-effects) it seems reasonable to allow a board
> handler to return an error instead of resetting.

No.  Reset will never return.  It is supposed to hard reset the board,
which means crossing the point of no return.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"In matrimony, to hesitate is sometimes to be saved."        - Butler

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Moffett, Kyle D]

On Oct 19, 2011, at 16:35, Wolfgang Denk wrote:
> Dear "Moffett, Kyle D",
> 
> In message <7C2673D7-CC5C-490C-9809-06C9A207154F@boeing.com> you wrote:
>> 
>> Since "reset" is basically just like any other U-Boot shell command,
> 
> No, it ain't.
> 
>> (except with some side-effects) it seems reasonable to allow a board
>> handler to return an error instead of resetting.
> 
> No.  Reset will never return.  It is supposed to hard reset the board,
> which means crossing the point of no return.

Ok.

By that definition, my board cannot safely use U-Boot's "reset" command.

Would you accept a patch which makes it possible for a board to not
implement a "reset" command at all?

There are a few places in common/cmd_bootm.c which are converted to use
panic("...") instead of printf("...")+do_reset().

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Mike Frysinger]

On Wednesday 19 October 2011 17:05:12 Moffett, Kyle D wrote:
> On Oct 19, 2011, at 16:35, Wolfgang Denk wrote:
> > Moffett, Kyle D wrote:
> >> Since "reset" is basically just like any other U-Boot shell command,
> > 
> > No, it ain't.
> > 
> >> (except with some side-effects) it seems reasonable to allow a board
> >> handler to return an error instead of resetting.
> > 
> > No.  Reset will never return.  It is supposed to hard reset the board,
> > which means crossing the point of no return.
> 
> Ok.
> 
> By that definition, my board cannot safely use U-Boot's "reset" command.
> 
> Would you accept a patch which makes it possible for a board to not
> implement a "reset" command at all?
> 
> There are a few places in common/cmd_bootm.c which are converted to use
> panic("...") instead of printf("...")+do_reset().

i guess i'm dumb, but i don't understand why it can't be made to work on your 
board.  but worse comes to worse, you could have your board reset call hang() 
or panic() ...
-mike
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[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Moffett, Kyle D]

On Oct 19, 2011, at 17:55, Mike Frysinger wrote:
> On Wednesday 19 October 2011 17:05:12 Moffett, Kyle D wrote:
>> On Oct 19, 2011, at 16:35, Wolfgang Denk wrote:
>>> Moffett, Kyle D wrote:
>>>> Since "reset" is basically just like any other U-Boot shell command,
>>> 
>>> No, it ain't.
>>> 
>>>> (except with some side-effects) it seems reasonable to allow a board
>>>> handler to return an error instead of resetting.
>>> 
>>> No.  Reset will never return.  It is supposed to hard reset the board,
>>> which means crossing the point of no return.
>> 
>> Ok.
>> 
>> By that definition, my board cannot safely use U-Boot's "reset" command.
>> 
>> Would you accept a patch which makes it possible for a board to not
>> implement a "reset" command at all?
>> 
>> There are a few places in common/cmd_bootm.c which are converted to use
>> panic("...") instead of printf("...")+do_reset().
> 
> i guess i'm dumb, but i don't understand why it can't be made to work on your 
> board.  but worse comes to worse, you could have your board reset call hang() 
> or panic() ...

Each board has two separate processor units on it, each with their own memory
and devices.  If either processor reboots on its own then both will hang and
be unusable.

So U-Boot MUST NOT reset without negotiating, even if the current CPU has
crashed, as that will cause the other (possibly perfectly operational) CPU to
also crash.

I suppose in theory I could add the __board_restart() hook and make it call
"panic()", but by removing do_reset() entirely for my board, I get helpful
link errors for tracking down places which should be calling panic() or
whatever instead.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Mike Frysinger]

On Wednesday 19 October 2011 18:52:10 Moffett, Kyle D wrote:
> So U-Boot MUST NOT reset without negotiating, even if the current CPU has
> crashed, as that will cause the other (possibly perfectly operational) CPU
> to also crash.

so why can't you have your do_reset() board hook negotiate with the other CPU 
to reset the system ?
-mike
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[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Moffett, Kyle D]

On Oct 19, 2011, at 20:15, Mike Frysinger wrote:
> On Wednesday 19 October 2011 18:52:10 Moffett, Kyle D wrote:
>> So U-Boot MUST NOT reset without negotiating, even if the current CPU has
>> crashed, as that will cause the other (possibly perfectly operational) CPU
>> to also crash.
> 
> so why can't you have your do_reset() board hook negotiate with the other CPU 
> to reset the system ?

That's what I originally implemented.  The problem is the negotiation can take
an unbounded amount of time to execute, so if it's run from the command line
then it needs to be interruptible (EG: with Ctrl-C), which means it needs to
be able to return an error.

I can see if I can come up with yet another possible alternative, but I'd like
to try to get the less-controversial patches (especially the GPIO header and
the e1000 ones) merged first.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Mike Frysinger]

On Wednesday 19 October 2011 20:23:15 Moffett, Kyle D wrote:
> On Oct 19, 2011, at 20:15, Mike Frysinger wrote:
> > On Wednesday 19 October 2011 18:52:10 Moffett, Kyle D wrote:
> >> So U-Boot MUST NOT reset without negotiating, even if the current CPU
> >> has crashed, as that will cause the other (possibly perfectly
> >> operational) CPU to also crash.
> > 
> > so why can't you have your do_reset() board hook negotiate with the other
> > CPU to reset the system ?
> 
> That's what I originally implemented.  The problem is the negotiation can
> take an unbounded amount of time to execute, so if it's run from the
> command line then it needs to be interruptible (EG: with Ctrl-C), which
> means it needs to be able to return an error.

what's wrong with an unbounded amount of time ?  if the user wants it to 
reset, then it should do so regardless of how long.
-mike
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[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Wolfgang Denk]

Dear "Moffett, Kyle D",

In message <8B4AC84D-1F22-4326-B75A-FB3CC39A5CF7@boeing.com> you wrote:
>
> By that definition, my board cannot safely use U-Boot's "reset" command.

You can call halt() or panic() as last stage of your reset
implementation.


Heh. Mike writes the same ;-)

> Would you accept a patch which makes it possible for a board to not
> implement a "reset" command at all?
> 
> There are a few places in common/cmd_bootm.c which are converted to use
> panic("...") instead of printf("...")+do_reset().

This is not acceptable, as changes behaviour: panic() will halt the
system, not reset it.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Actual war is a very messy business. Very, very messy business.
	-- Kirk, "A Taste of Armageddon", stardate 3193.0

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Wolfgang Denk]

Dear "Moffett, Kyle D",

In message <510974E8-A0C8-4E81-A034-B52F2AED12D0@boeing.com> you wrote:
>
> > so why can't you have your do_reset() board hook negotiate with the other CPU 
> > to reset the system ?
>
> That's what I originally implemented.  The problem is the negotiation can take
> an unbounded amount of time to execute, so if it's run from the command line
> then it needs to be interruptible (EG: with Ctrl-C), which means it needs to
> be able to return an error.

Why would it need to be interruptable?  When you type "reset", then
you are gone.  You cannot interrupt that command any more.

If it takes a long time like in your case, so you might print a
message "Please stand by / have a cup of coffee while resetting" or
so...

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I think they're going to take all this money that we  spend  now  on
war and death --"                   "And make them spend it on life."
	-- Edith Keeler and Kirk, "The City on the Edge of Forever",
	   stardate unknown.

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Moffett, Kyle D]

On Oct 20, 2011, at 10:02, Wolfgang Denk wrote:
> Dear "Moffett, Kyle D",
> In message <8B4AC84D-1F22-4326-B75A-FB3CC39A5CF7@boeing.com> you wrote:
>> 
>> Would you accept a patch which makes it possible for a board to not
>> implement a "reset" command at all?
>> 
>> There are a few places in common/cmd_bootm.c which are converted to use
>> panic("...") instead of printf("...")+do_reset().
> 
> This is not acceptable, as changes behaviour: panic() will halt the
> system, not reset it.

That is obviously wrong, as a 5 second glance at panic() in the file
lib/vsprintf.c would tell you.  For 540 of the 567 board configs in
the include/configs/ directory, panic will directly call do_reset();
only 27 of the configs (less than 5%) set CONFIG_PANIC_HANG.

The only change with the patch for boards without CONFIG_PANIC_HANG is
that panic() has an extra udelay() to ensure that the serial console
messages go out before the reset.

For the boards that *do* set CONFIG_PANIC_HANG, none of the fatal
errors in common/cmd_bootm.c should cause U-Boot to reset, they are
all valid panic() conditions, such as GZIP overwrite errors and fatal
image format issues.  In those cases this is also a bugfix.

Patch to follow shortly.

Cheers,
Kyle Moffett

--
Curious about my work on the Debian powerpcspe port?
I'm keeping a blog here: http://pureperl.blogspot.com/

[U-Boot] [PATCH 2/3] mpc85xx: Add a board-specific restart hook

[Wolfgang Denk]

Dear "Moffett, Kyle D",

In message <5BF60315-656D-4173-8722-9E2EC99AAEDE@boeing.com> you wrote:
>
> For the boards that *do* set CONFIG_PANIC_HANG, none of the fatal
> errors in common/cmd_bootm.c should cause U-Boot to reset, they are
> all valid panic() conditions, such as GZIP overwrite errors and fatal
> image format issues.  In those cases this is also a bugfix.

These boards may rely on such behaviour, for example by then booting
an altenative image.  This _is_ a change of behavior, even if only for
a relatively small number of boards.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are always alternatives.
	-- Spock, "The Galileo Seven", stardate 2822.3

[U-Boot] [PATCH 2/3] mpc85xx: Add inline GPIO acessor functions

[Kumar Gala]

On Oct 19, 2011, at 1:58 PM, Kyle Moffett wrote:

> To ease the implementation of other MPC85xx board ports, several common
> GPIO helpers are added to <asm/mpc85xx_gpio.h>.
> 
> Since each of these compiles to no more than 4-5 instructions it would
> be very inefficient to call them out of line, therefore we put them
> entirely in the header file.
> 
> The HWW-1U-1A board port which these were written for strongly prefers
> to set multiple GPIOs as a single batch operation, so the API is
> designed around that basis.
> 
> To assist other board ports, a small set of wrappers are used which
> provides a standard gpio_request() interface around the MPC85xx-specific
> functions.  This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO
> 
> Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Kumar Gala <kumar.gala@freescale.com>
> Cc: Peter Tyser <ptyser@xes-inc.com>
> 
> --
> 
> Changelog:
> v2: Moved the inline functions to a non-board-specific header
> v3: Added generic Linux-standard GPIO wrappers
> v4: Improved comments and fixed minor bugs in the wrapper functions
> v5: No changes
> v6: Rebased onto the 'next' branch of git://git.denx.de/u-boot-mpc85xx.git
> v7: No changes
> v8: Rebased onto latest HEAD and add README entry for the config option
> v9: Removed CONFIG_* option and added missing #ifdef protection
> ---
> arch/powerpc/include/asm/mpc85xx_gpio.h |  123 +++++++++++++++++++++++++++++++
> 1 files changed, 123 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/include/asm/mpc85xx_gpio.h

applied to 85xx

- k