[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

[Anton Staaf]

ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel.  It is
used to define the minimum alignement requirement for a DMA buffer.  This
series of patches ensures that it will always be defined in the arch specific
asm/cache.h header and that asm/cache.h is included in common.h.  I chose to
add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
reasons.  First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
and thus to use it I would have to first define it correctly for all used
architectures.  I wasn't quite up to that task right now.  Defining
ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
allow it to be the maximum cacheline size known for an architecture.  And
secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
to align DMA buffers.  In particular, on cache coherent architectures you can
define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
such as PCI alignment requirements).

This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE.  I will
repost those patches based on this set shortly.

Since we've heard no complaints and have an ack for PowerPC at least, I think
this can go in as is.  It's defining a new macro that isn't used yet and I
believe that each architecture has a reasonable value defined now.

Thanks,
    Anton

Changes in v2:
- Remove blackfin patches in favor of Mike's import of the Linux kernel cache.h
- Remove all Gerrit Change-ID tags

Anton Staaf (11):
  arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
  cache: include asm/cache.h for ARCH_DMA_MINALIGN definition

 arch/arm/include/asm/cache.h        |   11 +++++++++
 arch/avr32/include/asm/cache.h      |   40 +++++++++++++++++++++++++++++++++++
 arch/m68k/include/asm/cache.h       |   10 ++++++++
 arch/microblaze/include/asm/cache.h |   37 ++++++++++++++++++++++++++++++++
 arch/mips/include/asm/cache.h       |   36 +++++++++++++++++++++++++++++++
 arch/nios2/include/asm/cache.h      |   11 +++++++++
 arch/powerpc/include/asm/cache.h    |    6 +++++
 arch/sh/include/asm/cache.h         |   17 ++++++++++++++
 arch/sparc/include/asm/cache.h      |   10 ++++++++
 arch/x86/include/asm/cache.h        |   35 ++++++++++++++++++++++++++++++
 include/common.h                    |    8 +++++++
 11 files changed, 221 insertions(+), 0 deletions(-)
 create mode 100644 arch/avr32/include/asm/cache.h
 create mode 100644 arch/microblaze/include/asm/cache.h
 create mode 100644 arch/mips/include/asm/cache.h
 create mode 100644 arch/x86/include/asm/cache.h

-- 
1.7.3.1

[U-Boot] [PATCH v2 01/11] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/include/asm/cache.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index d0518be..eef6a5a 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
 #endif /* _ASM_CACHE_H */
-- 
1.7.3.1

[U-Boot] [PATCH v2 02/11] m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
---
 arch/m68k/include/asm/cache.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 7c84e48..5c9bb30 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -207,4 +207,14 @@ void dcache_invalid(void);
 
 #endif
 
+/*
+ * m68k uses 16 byte L1 data cache line sizes.  Use this for DMA buffer
+ * alignment unless the board configuration has specified a new value.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
+
 #endif				/* __CACHE_H */
-- 
1.7.3.1

[U-Boot] [PATCH v2 03/11] nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
---
 arch/nios2/include/asm/cache.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h
index c78f343..2cc16e4 100644
--- a/arch/nios2/include/asm/cache.h
+++ b/arch/nios2/include/asm/cache.h
@@ -27,4 +27,15 @@
 extern void flush_dcache (unsigned long start, unsigned long size);
 extern void flush_icache (unsigned long start, unsigned long size);
 
+/*
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
+ * bytes.  If the board configuration has not specified one we default to the
+ * largest of these values for alignment of DMA buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
 #endif /* __ASM_NIOS2_CACHE_H_ */
-- 
1.7.3.1

[U-Boot] [PATCH v2 04/11] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
 arch/powerpc/include/asm/cache.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05..e6b8f69 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -21,6 +21,12 @@
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
 /*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
+/*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */
 #ifndef CONFIG_SYS_CACHELINE_SIZE
-- 
1.7.3.1

[U-Boot] [PATCH v2 05/11] sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 arch/sh/include/asm/cache.h |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 2cfc0a7..6ffab4d 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -6,6 +6,7 @@
 int cache_control(unsigned int cmd);
 
 #define L1_CACHE_BYTES 32
+
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
@@ -30,6 +31,22 @@ void dcache_invalid_range(u32 start, u32 end)
 			      : "m" (__m(v)));
 	}
 }
+#else
+
+/*
+ * 32-bytes is the largest L1 data cache line size for SH the architecture.  So
+ * it is a safe default for DMA alignment.
+ */
+#define ARCH_DMA_MINALIGN	32
+
 #endif /* CONFIG_SH4 || CONFIG_SH4A */
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on SH.
+ */
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+#endif
+
 #endif	/* __ASM_SH_CACHE_H */
-- 
1.7.3.1

[U-Boot] [PATCH v2 06/11] sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
---
 arch/sparc/include/asm/cache.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 03e8d94..44870e8 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -28,4 +28,14 @@
 #include <linux/config.h>
 #include <asm/processor.h>
 
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
+ * use 32-bytes, the cacheline size for Sparc.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
 #endif
-- 
1.7.3.1

[U-Boot] [PATCH v2 07/11] avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
---
 arch/avr32/include/asm/cache.h |   40 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)
 create mode 100644 arch/avr32/include/asm/cache.h

diff --git a/arch/avr32/include/asm/cache.h b/arch/avr32/include/asm/cache.h
new file mode 100644
index 0000000..3b2b032
--- /dev/null
+++ b/arch/avr32/include/asm/cache.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AVR32_CACHE_H__
+#define __AVR32_CACHE_H__
+
+/*
+ * Since the AVR32 architecture has a queryable cacheline size with a maximum
+ * value of 256 we set the DMA buffer alignemnt requirement to this maximum
+ * value.  The board config can override this if it knows that the cacheline
+ * size is a smaller value.  AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
+ * macro to specify cache line size, so if it is set we use it instead.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#elif defined(CONFIG_SYS_DCACHE_LINESZ)
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_DCACHE_LINESZ
+#else
+#define ARCH_DMA_MINALIGN	256
+#endif
+
+#endif /* __AVR32_CACHE_H__ */
-- 
1.7.3.1

[U-Boot] [PATCH v2 08/11] microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/include/asm/cache.h |   37 +++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 arch/microblaze/include/asm/cache.h

diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
new file mode 100644
index 0000000..0373e88
--- /dev/null
+++ b/arch/microblaze/include/asm/cache.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MICROBLAZE_CACHE_H__
+#define __MICROBLAZE_CACHE_H__
+
+/*
+ * The microblaze can have either a 4 or 16 byte cacheline depending on whether
+ * you are using OPB(4) or CacheLink(16).  If the board config has not specified
+ * a cacheline size we assume the larger value of 16 bytes for DMA buffer
+ * alignment.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
+
+#endif /* __MICROBLAZE_CACHE_H__ */
-- 
1.7.3.1

[U-Boot] [PATCH v2 09/11] mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
---
 arch/mips/include/asm/cache.h |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/cache.h

diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 0000000..5406d5d
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIPS_CACHE_H__
+#define __MIPS_CACHE_H__
+
+/*
+ * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
+ * that as a default for aligning DMA buffers unless the board config has
+ * specified another cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	128
+#endif
+
+#endif /* __MIPS_CACHE_H__ */
-- 
1.7.3.1

[U-Boot] [PATCH v2 10/11] x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Graeme Russ <graeme.russ@gmail.com>
---
 arch/x86/include/asm/cache.h |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/include/asm/cache.h

diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
new file mode 100644
index 0000000..87c9e0b
--- /dev/null
+++ b/arch/x86/include/asm/cache.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __X86_CACHE_H__
+#define __X86_CACHE_H__
+
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
+ * use 64-bytes, a safe default for x86.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
+#endif /* __X86_CACHE_H__ */
-- 
1.7.3.1

[U-Boot] [PATCH v2 11/11] cache: include asm/cache.h for ARCH_DMA_MINALIGN definition

[Anton Staaf]

ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are
aligned correctly.  In all current cases this means that the DMA
buffer will be aligned to at least the L1 data cache line size of
the configured architecture.  If the board configuration file
does not specify the architecture L1 data cache line size then the
maximum line size of the architecture is used to align DMA buffers.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Laurence Withers <lwithers@guralp.com>
---
 include/common.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index a55600b..3a6ef0e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -813,6 +813,14 @@ int cpu_release(int nr, int argc, char * const argv[]);
 #define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
 
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
 /* Pull in stuff for the build system */
 #ifdef DO_DEPS_ONLY
 # include <environment.h>
-- 
1.7.3.1

[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

[Anton Staaf]

On Mon, Oct 17, 2011 at 4:46 PM, Anton Staaf <robotboy@chromium.org> wrote:
> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. ?It is
> used to define the minimum alignement requirement for a DMA buffer. ?This
> series of patches ensures that it will always be defined in the arch specific
> asm/cache.h header and that asm/cache.h is included in common.h. ?I chose to
> add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
> reasons. ?First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
> and thus to use it I would have to first define it correctly for all used
> architectures. ?I wasn't quite up to that task right now. ?Defining
> ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
> allow it to be the maximum cacheline size known for an architecture. ?And
> secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
> to align DMA buffers. ?In particular, on cache coherent architectures you can
> define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
> such as PCI alignment requirements).
>
> This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
> modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE. ?I will
> repost those patches based on this set shortly.
>
> Since we've heard no complaints and have an ack for PowerPC at least, I think
> this can go in as is. ?It's defining a new macro that isn't used yet and I
> believe that each architecture has a reasonable value defined now.
>
> Thanks,
> ? ?Anton
>
> Changes in v2:
> - Remove blackfin patches in favor of Mike's import of the Linux kernel cache.h
> - Remove all Gerrit Change-ID tags

I have now run MAKEALL for both ARMv7a and PowerPC successfully.
There were a number of
build failures for "powerpc", but no new ones given my patch.  I'd
like to land this soon
so I can get to landing the fixes for the unaligned buffers in U-Boot.

Thanks,
    Anton

> Anton Staaf (11):
> ?arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ?cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
>
> ?arch/arm/include/asm/cache.h ? ? ? ?| ? 11 +++++++++
> ?arch/avr32/include/asm/cache.h ? ? ?| ? 40 +++++++++++++++++++++++++++++++++++
> ?arch/m68k/include/asm/cache.h ? ? ? | ? 10 ++++++++
> ?arch/microblaze/include/asm/cache.h | ? 37 ++++++++++++++++++++++++++++++++
> ?arch/mips/include/asm/cache.h ? ? ? | ? 36 +++++++++++++++++++++++++++++++
> ?arch/nios2/include/asm/cache.h ? ? ?| ? 11 +++++++++
> ?arch/powerpc/include/asm/cache.h ? ?| ? ?6 +++++
> ?arch/sh/include/asm/cache.h ? ? ? ? | ? 17 ++++++++++++++
> ?arch/sparc/include/asm/cache.h ? ? ?| ? 10 ++++++++
> ?arch/x86/include/asm/cache.h ? ? ? ?| ? 35 ++++++++++++++++++++++++++++++
> ?include/common.h ? ? ? ? ? ? ? ? ? ?| ? ?8 +++++++
> ?11 files changed, 221 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/avr32/include/asm/cache.h
> ?create mode 100644 arch/microblaze/include/asm/cache.h
> ?create mode 100644 arch/mips/include/asm/cache.h
> ?create mode 100644 arch/x86/include/asm/cache.h
>
> --
> 1.7.3.1
>
>

[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

[Wolfgang Denk]

Dear Anton Staaf,

In message <CAF6FioXuWF5ar4G9x6JsHw0n6VyWE=6o5zj0m8DePOsOt7hsKQ@mail.gmail.com> you wrote:
>
> I have now run MAKEALL for both ARMv7a and PowerPC successfully.
> There were a number of
> build failures for "powerpc", but no new ones given my patch.  I'd
> like to land this soon
> so I can get to landing the fixes for the unaligned buffers in U-Boot.

Um...

1e41f5a   2011-10-23 20:50:43 +0200   cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
3620f86   2011-10-23 20:50:43 +0200   x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
72d4dd4   2011-10-23 20:50:43 +0200   mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
ee729af   2011-10-23 20:50:43 +0200   microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
75ff24b   2011-10-23 20:50:42 +0200   avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
3c3f8a7   2011-10-23 20:50:42 +0200   sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
2482e3c   2011-10-23 20:50:42 +0200   sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
0991701   2011-10-23 20:50:42 +0200   powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
6fa6035   2011-10-23 20:50:42 +0200   nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
a8fc12e   2011-10-23 20:50:42 +0200   m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
44d6cbb   2011-10-23 20:50:42 +0200   arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Isn't this what you are asking for?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
        Ordnung ist die Lust der Vernunft,
        aber Unordnung die Wonne der Phantasie         - Paul Claudel

[U-Boot] [PATCH v2 00/11] Define ARCH_DMA_MINALIGN for all architectures

[Anton Staaf]

On Mon, Oct 24, 2011 at 12:45 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Anton Staaf,
>
> In message <CAF6FioXuWF5ar4G9x6JsHw0n6VyWE=6o5zj0m8DePOsOt7hsKQ@mail.gmail.com> you wrote:
>>
>> I have now run MAKEALL for both ARMv7a and PowerPC successfully.
>> There were a number of
>> build failures for "powerpc", but no new ones given my patch. ?I'd
>> like to land this soon
>> so I can get to landing the fixes for the unaligned buffers in U-Boot.
>
> Um...
>
> 1e41f5a ? 2011-10-23 20:50:43 +0200 ? cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
> 3620f86 ? 2011-10-23 20:50:43 +0200 ? x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 72d4dd4 ? 2011-10-23 20:50:43 +0200 ? mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> ee729af ? 2011-10-23 20:50:43 +0200 ? microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 75ff24b ? 2011-10-23 20:50:42 +0200 ? avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 3c3f8a7 ? 2011-10-23 20:50:42 +0200 ? sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 2482e3c ? 2011-10-23 20:50:42 +0200 ? sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 0991701 ? 2011-10-23 20:50:42 +0200 ? powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 6fa6035 ? 2011-10-23 20:50:42 +0200 ? nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> a8fc12e ? 2011-10-23 20:50:42 +0200 ? m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
> 44d6cbb ? 2011-10-23 20:50:42 +0200 ? arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
>
> Isn't this what you are asking for?

Hah.  :)  Yes, I don't know why I missed those going in.

I'll start reworking the other patches and send them shortly.

Thanks again,
    Anton

> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> ? ? ? ?Ordnung ist die Lust der Vernunft,
> ? ? ? ?aber Unordnung die Wonne der Phantasie ? ? ? ? - Paul Claudel
>