From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Frysinger Date: Sun, 6 Nov 2011 20:09:08 -0500 Subject: [U-Boot] [PATCH] ARM: Generic cache ops skeleton In-Reply-To: References: <1320542183-20309-1-git-send-email-marek.vasut@gmail.com> <201111061907.30014.marek.vasut@gmail.com> Message-ID: <201111062009.09468.vapier@gentoo.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sunday 06 November 2011 14:29:47 Simon Glass wrote: > On this particular patch, I feel it should be more explicit about L1 > cache, which is what I think it deals with. We may want to support L2 > also through a similar API. And a CONFIG option is a good idea. the point of flushing caches is to make the memory coherent to other devices (like peripherals). we don't differentiate between the cache levels. > Finally, even the CP15/cache/MMU code is duplicated in different > arch/arm/cpu subdirs. Can we unify this a bit? things should be separated based on core and system levels. the fact that a particular SoC is say armv4 doesn't mean it should have armv4 specific cache/mmu handling in its SoC subdir. i think the Linux arm tree is properly separating things. -mike -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: This is a digitally signed message part. Url : http://lists.denx.de/pipermail/u-boot/attachments/20111106/5626c6b9/attachment.pgp