[U-Boot] Is CCSRBAR relocation broken on P2020?

[Ira W. Snyder <iws@ovro.caltech.edu>]

On Thu, Nov 10, 2011 at 07:24:00PM +0000, McClintock Matthew-B29882 wrote:
> On Thu, Nov 10, 2011 at 11:47 AM, Timur Tabi <timur@freescale.com> wrote:
> >> I boot off of SDCARD (P2020COME_SDCARD_config). To write the U-Boot
> >> image to the microSD card, I use a tool provided with the BSP called
> >> "boot_format-1.0.0". Maybe you are familiar with it?
> >
> > I think that qualifies as multi-stage booting. ?The SD card is not mapped at address fff00000 at POR time, which is needed to boot a single-stage U-Boot. ?Therefore, you must have a multi-stage U-Boot.
> >
> > I'm not familiar with boot_format-1.0.0, but my guess is that it creates the pre-boot loader.
> 
> Timur,
> 
> Did you test your CCSRBAR changes with a board that uses the on chip
> rom as well as L2SRAM to boot? Does the COME board load from SDCARD to
> DDR or to L2SRAM? I suspect it's L2SRAM since this board has 512kB
> which is large enough for a stock u-boot image.
> 

I boot using the on-chip ROM, loading U-Boot from SD card to DDR. The
configuration file I was provided for boot_format-1.0.0 uses DDR, so it
is what I have continued to use. I remember seeing a comment somewhere
saying that the L2 doesn't work on P2020 due to some hardware problem,
though I cannot find that comment at the moment.

My configuration for boot_format is attached. The configuration is
described in the P2020RM (section 4.5) and Freescale Document Number
AN3659, titled "Booting from On-Chip ROM (eSHDC or eSPI)" section 2.5.1.

My configuration is attached. I'm happy to test using the L2SRAM
instead, if I can figure out what to change in the attached
configuration file.

Thanks,
Ira
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