[U-Boot] [PATCH v3 2/2] mpc85xx: support for Freescale COM Express P2020

[Ira W. Snyder <iws@ovro.caltech.edu>]

On Fri, Nov 11, 2011 at 08:36:47PM +0000, McClintock Matthew-B29882 wrote:
> On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > Yep, this is a P2020.
> >
> > I'll check the Freescale documentation. Hopefully it provides an example
> > of how to configure the On-Chip ROM to use L2SRAM instead of DDR.
> >
> > I'll try and find a U-Boot port that configures DDR via SPD. I'm sure
> > there are plenty, however any hints are welcome. :)
> 
> For an example the P2020DS works like this... I've attached the
> boot-format dat file as well.
> 

Thanks. That config_sram.dat is exactly what I came up with.

I have my board booting via L2SRAM, but the DDR doesn't get configured
correctly yet. I'm trying to figure out how the DDR SPD stuff works in
U-Boot. I've never used it before. I'm following the P2020DS code as an
example, but I haven't yet figured out how the code in
board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
structure especially).

Ira