From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 25 Nov 2011 09:45:03 +0100 Subject: [U-Boot] [PATCH 06/11] MIPS: make cache operation mode configurable in dcache_enable() In-Reply-To: <1322143076-20349-7-git-send-email-daniel.schwierzeck@googlemail.com> References: <1322143076-20349-1-git-send-email-daniel.schwierzeck@googlemail.com> <1322143076-20349-7-git-send-email-daniel.schwierzeck@googlemail.com> Message-ID: <201111250945.04110.marek.vasut@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to > use the new config option in dcache_enable(). > > Fix this to avoid inconsistencies if someone wants to disable > and enable D-caches. > > Signed-off-by: Daniel Schwierzeck > --- > arch/mips/cpu/mips32/cache.S | 6 +++++- > 1 files changed, 5 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S > index 5ce0ec4..e683e8b 100644 > --- a/arch/mips/cpu/mips32/cache.S > +++ b/arch/mips/cpu/mips32/cache.S > @@ -30,6 +30,10 @@ > #include > #include > > +#ifndef CONFIG_SYS_MIPS_CACHE_MODE > +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT > +#endif > + > #define RA t8 > > /* > @@ -224,7 +228,7 @@ LEAF(dcache_enable) > mfc0 t0, CP0_CONFIG > ori t0, CONF_CM_CMASK > xori t0, CONF_CM_CMASK > - ori t0, CONF_CM_CACHABLE_NONCOHERENT > + ori t0, CONFIG_SYS_MIPS_CACHE_MODE > mtc0 t0, CP0_CONFIG > jr ra > END(dcache_enable) Acked-by: Marek Vasut