* [U-Boot] Attempts to make U-Boot start from L2 Cache on P2020RDB-like board
@ 2011-11-28 22:22 Wojciech Zabolotny
2011-11-28 22:59 ` Ira W. Snyder
0 siblings, 1 reply; 3+ messages in thread
From: Wojciech Zabolotny @ 2011-11-28 22:22 UTC (permalink / raw)
To: u-boot
Hi,
I'm trying to achieve starting of U-Boot from L2 cache memory after
downloading from SD card.
The board is P2020RDB-like, however it contains only 512MB of memory.
Because we suspect, that there may be problems with DDR memory, we
wanted at least to get U-Boot starting from L2 cache configured as
SRAM.
Finally I got the U-boot starting and displaying the first messages via UART:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
U-Boot 2011.09-01153-gdca61f0-dirty (Nov 28 2011 - 15:35:03)
CPU0: P2020E, Version: 2.0, (0x80ea0020)
Core: E500, Version: 5.0, (0x80211050)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz,
CCB:600 MHz,
DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P2020RDB RevD
I2C: ready
SPI: ready
DRAM: Configuring DDR for 666.667 MT/s data rate
1 GiB (DDR2, 64-bit, CL=5, ECC off)
NOR Flash Bank : Primary
SD/MMC : 4-bit Mode
eSPI : Enabled
Flash: 16 MiB
L2: 512 KB enabled
NAND: 32 MiB
MMC: FSL_ESDHC: 0
Data Read Failed in PIO Mode.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To achieve that I had to withdraw the patch described in:
http://lists.denx.de/pipermail/u-boot/2011-March/088279.html
I also had to change the CONFIG_SYS_TEXT_BASE in P1_P2_RDB.h :
64,65c64,65
< #define CONFIG_SYS_TEXT_BASE 0xf8f80000
< #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
---
> #define CONFIG_SYS_TEXT_BASE 0x11000000
> #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
70,71c70,71
< #define CONFIG_SYS_TEXT_BASE 0xf8f80000
< #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
---
> #define CONFIG_SYS_TEXT_BASE 0x11000000
> #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
The u-boot was compiled with
make P2020RDB_SDCARD_config
make
The config for boot_format was:
40:424f4f54
44:00000000
48:00080000
4c:00000000
50:00001000
54:00000000
58:f8f80000
5c:00000000
60:f8fff000
64:00000000
68:00000006
80:ff720100
84:f8f80000
88:ff720e44
8c:0000000c
90:ff720000
94:80010000
98:ff72e40c
9c:00000040
a0:40000001
a4:00000100
a8:80000001
ac:80000001
It seems that the U-Boot somehow misconfigures the SD controller.
The first part of U-Boot is loading correctly and the initial messages
are displayed,
but when it tries to continue downloading, it displays the "Data Read
Failed in PIO Mode."
and hangs.
I will appreciate any further pointers...
--
TIA & Regards,
Wojciech M. Zabolotny
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] Attempts to make U-Boot start from L2 Cache on P2020RDB-like board
2011-11-28 22:22 [U-Boot] Attempts to make U-Boot start from L2 Cache on P2020RDB-like board Wojciech Zabolotny
@ 2011-11-28 22:59 ` Ira W. Snyder
2011-11-29 10:40 ` Wojciech Zabolotny
0 siblings, 1 reply; 3+ messages in thread
From: Ira W. Snyder @ 2011-11-28 22:59 UTC (permalink / raw)
To: u-boot
On Mon, Nov 28, 2011 at 11:22:01PM +0100, Wojciech Zabolotny wrote:
> Hi,
> I'm trying to achieve starting of U-Boot from L2 cache memory after
> downloading from SD card.
> The board is P2020RDB-like, however it contains only 512MB of memory.
> Because we suspect, that there may be problems with DDR memory, we
> wanted at least to get U-Boot starting from L2 cache configured as
> SRAM.
>
> Finally I got the U-boot starting and displaying the first messages via UART:
> vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
> U-Boot 2011.09-01153-gdca61f0-dirty (Nov 28 2011 - 15:35:03)
>
> CPU0: P2020E, Version: 2.0, (0x80ea0020)
> Core: E500, Version: 5.0, (0x80211050)
> Clock Configuration:
> CPU0:1200 MHz, CPU1:1200 MHz,
> CCB:600 MHz,
> DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
> L1: D-cache 32 kB enabled
> I-cache 32 kB enabled
> Board: P2020RDB RevD
> I2C: ready
> SPI: ready
> DRAM: Configuring DDR for 666.667 MT/s data rate
> 1 GiB (DDR2, 64-bit, CL=5, ECC off)
> NOR Flash Bank : Primary
> SD/MMC : 4-bit Mode
> eSPI : Enabled
> Flash: 16 MiB
> L2: 512 KB enabled
> NAND: 32 MiB
> MMC: FSL_ESDHC: 0
>
> Data Read Failed in PIO Mode.
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> To achieve that I had to withdraw the patch described in:
> http://lists.denx.de/pipermail/u-boot/2011-March/088279.html
>
> I also had to change the CONFIG_SYS_TEXT_BASE in P1_P2_RDB.h :
> 64,65c64,65
> < #define CONFIG_SYS_TEXT_BASE 0xf8f80000
> < #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
> ---
> > #define CONFIG_SYS_TEXT_BASE 0x11000000
> > #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
> 70,71c70,71
> < #define CONFIG_SYS_TEXT_BASE 0xf8f80000
> < #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
> ---
> > #define CONFIG_SYS_TEXT_BASE 0x11000000
> > #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
>
>
> The u-boot was compiled with
> make P2020RDB_SDCARD_config
> make
>
> The config for boot_format was:
> 40:424f4f54
> 44:00000000
> 48:00080000
> 4c:00000000
> 50:00001000
> 54:00000000
> 58:f8f80000
> 5c:00000000
> 60:f8fff000
> 64:00000000
> 68:00000006
>
> 80:ff720100
> 84:f8f80000
> 88:ff720e44
> 8c:0000000c
> 90:ff720000
> 94:80010000
> 98:ff72e40c
> 9c:00000040
> a0:40000001
> a4:00000100
> a8:80000001
> ac:80000001
>
> It seems that the U-Boot somehow misconfigures the SD controller.
> The first part of U-Boot is loading correctly and the initial messages
> are displayed,
> but when it tries to continue downloading, it displays the "Data Read
> Failed in PIO Mode."
> and hangs.
> I will appreciate any further pointers...
I ran into this issue on the P2020COME board recently. I think the
include/configs/P1_P2_RDB.h file isn't correct for P2020.
Try removing the 3 lines:
#ifdef CONFIG_P2020
#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional */
#endif
And add this line in their place:
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Let me know if that helps. PIO mode was broken on my P2020, DMA mode
worked.
Ira
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] Attempts to make U-Boot start from L2 Cache on P2020RDB-like board
2011-11-28 22:59 ` Ira W. Snyder
@ 2011-11-29 10:40 ` Wojciech Zabolotny
0 siblings, 0 replies; 3+ messages in thread
From: Wojciech Zabolotny @ 2011-11-29 10:40 UTC (permalink / raw)
To: u-boot
On Mon, Nov 28, 2011 at 11:59 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> On Mon, Nov 28, 2011 at 11:22:01PM +0100, Wojciech Zabolotny wrote:
[...]
>> It seems that the U-Boot somehow misconfigures the SD controller.
>> The first part of U-Boot is loading correctly and the initial messages
>> are displayed,
>> but when it tries to continue downloading, it displays the "Data Read
>> Failed in PIO Mode."
>> and hangs.
>> I will appreciate any further pointers...
>
> I ran into this issue on the P2020COME board recently. I think the
> include/configs/P1_P2_RDB.h file isn't correct for P2020.
>
> Try removing the 3 lines:
> #ifdef CONFIG_P2020
> #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional */
> #endif
>
> And add this line in their place:
> #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
>
> Let me know if that helps. PIO mode was broken on my P2020, DMA mode
> worked.
>
> Ira
Thanks a lot!
It really works. Now I have working U-Boot and can debug my DDR.
--
Wojtek
^ permalink raw reply [flat|nested] 3+ messages in thread
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2011-11-28 22:22 [U-Boot] Attempts to make U-Boot start from L2 Cache on P2020RDB-like board Wojciech Zabolotny
2011-11-28 22:59 ` Ira W. Snyder
2011-11-29 10:40 ` Wojciech Zabolotny
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