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From: Mike Frysinger <vapier@gentoo.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Date: Thu, 8 Dec 2011 01:25:48 -0500	[thread overview]
Message-ID: <201112080125.50896.vapier@gentoo.org> (raw)
In-Reply-To: <4EE05045.3000100@ti.com>

On Thursday 08 December 2011 00:51:01 Aneesh V wrote:
> On Thursday 08 December 2011 05:44 AM, Mike Frysinger wrote:
> > On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
> >> commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't
> >> execute on Tegra, due to the AVP (ARM7TDI) not having a CP15.
> >> Result was an undefined instruction hang just after reset.
> >> 
> >> --- a/arch/arm/cpu/armv7/start.S
> >> +++ b/arch/arm/cpu/armv7/start.S
> >> 
> >> +#if !defined(CONFIG_TEGRA2)
> >> 
> >>   /*
> >>   
> >>    * Setup vector:
> >>    * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
> >> 
> >> @@ -159,6 +160,7 @@ reset:
> >>   	ldr	r0, =_start
> >>   	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
> >>   
> >>   #endif
> >> 
> >> +#endif	/* !Tegra2 */
> > 
> > forgive my ignorance, but would it be better to invert the logic ?  have
> > ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and
> > then put all this logic behind that rather than grow a list of SoC's
> > that lack it ?
> 
> As far as I understand CP15 is typically available(if not mandatory) on
> all armv7 processors. Here, IIUC, NVidia has a peculiar architecture
> that necessitates an armv4 processor supported by armv7 code. IMHO,
> this is the exceptional case.

np then ... thanks
-mike
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  reply	other threads:[~2011-12-08  6:25 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-12-06 23:00 [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset Tom Warren
2011-12-08  0:14 ` Mike Frysinger
2011-12-08  5:51   ` Aneesh V
2011-12-08  6:25     ` Mike Frysinger [this message]
2011-12-08 15:37     ` Tom Warren
2011-12-09  6:18       ` Aneesh V
     [not found]         ` <7E91C59574E9954FA075F8D8CCDF78DB392E3A5798@HQMAIL04.nvidia.com>
2011-12-20 23:27           ` Tom Warren
2011-12-21  4:07             ` Simon Glass
2011-12-21  6:58             ` Wolfgang Denk
2011-12-21  8:02 ` Aneesh V
2011-12-21 16:10   ` Tom Warren
2011-12-21 19:37 ` Wolfgang Denk

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