From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Frysinger Date: Thu, 8 Dec 2011 01:25:48 -0500 Subject: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset In-Reply-To: <4EE05045.3000100@ti.com> References: <1323212419-21023-1-git-send-email-twarren@nvidia.com> <201112071914.32335.vapier@gentoo.org> <4EE05045.3000100@ti.com> Message-ID: <201112080125.50896.vapier@gentoo.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday 08 December 2011 00:51:01 Aneesh V wrote: > On Thursday 08 December 2011 05:44 AM, Mike Frysinger wrote: > > On Tuesday 06 December 2011 18:00:19 Tom Warren wrote: > >> commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't > >> execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. > >> Result was an undefined instruction hang just after reset. > >> > >> --- a/arch/arm/cpu/armv7/start.S > >> +++ b/arch/arm/cpu/armv7/start.S > >> > >> +#if !defined(CONFIG_TEGRA2) > >> > >> /* > >> > >> * Setup vector: > >> * (OMAP4 spl TEXT_BASE is not 32 byte aligned. > >> > >> @@ -159,6 +160,7 @@ reset: > >> ldr r0, =_start > >> mcr p15, 0, r0, c12, c0, 0 @Set VBAR > >> > >> #endif > >> > >> +#endif /* !Tegra2 */ > > > > forgive my ignorance, but would it be better to invert the logic ? have > > ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and > > then put all this logic behind that rather than grow a list of SoC's > > that lack it ? > > As far as I understand CP15 is typically available(if not mandatory) on > all armv7 processors. Here, IIUC, NVidia has a peculiar architecture > that necessitates an armv4 processor supported by armv7 code. IMHO, > this is the exceptional case. np then ... thanks -mike -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: This is a digitally signed message part. URL: