From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Fri, 6 Jan 2012 21:51:43 +0100
Subject: [U-Boot] Possible Denx m28evk ethernet problem + solution
In-Reply-To: <2C570823-D31F-4C9E-A2CA-8C68CBDA846C@delien.nl>
References: <3C18F794-D414-406A-BEA4-ABE59990B5BF@Delien.nl>
	<201201062005.15727.marek.vasut@gmail.com>
	<2C570823-D31F-4C9E-A2CA-8C68CBDA846C@delien.nl>
Message-ID: <201201062151.43616.marek.vasut@gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

> >> I'm currently working on U-Boot support for the Freescale i.mx28evk
> >> board.
> > 
> > This is already supported mainline.
> 
> Hm; my workspace is quite up-to-date, but I didn't find it. What
> configuration should I use for the Freescale i.mx28evk board?
> m28evk_config boots the board, but not much more. The difference between
> the Freescale i.mx28evk board and the Denx m28evk modules are too big (eg.
> ssp2 for mmc1, etc.)

make mx28evk_config? board/freescale/mx28evk
> 
> > The DENX board is actually ok, working properly,
> 
> I don't doubt the working of the Denx module; I'm sure it works fine, but I
> don't have one laying around, so I cannot check.

I did check, don't worry.

> However, the
> configuration for the Denx m28evk module doesn't work very well on the
> Freescale i.mx28evk board.

That's to be expected!
> 
> > you don't understand what's
> > going on in there.
> 
> No need to be harsh; I don't have a diagram of the Denx board, so I don't
> know what clock configuration was chosen for it's design.

Sorry, it wasn't meant to be too direct.
> 
> > The RMII mode of PHY supplies clock to CPU. Read the manual
> > before you start doing some wild acusations please :-)
> 
> On my board, there wasn't any clock signal between the SoC and the PHYs,
> regardless of who's supposed to source it. I can lift R171 and check who's
> supplying it after my modification, but I'm pretty sure it's the SoC. This
> situation works, but may still be wrong; No argument there. But this is
> the same situation as the old Freescale supplied u-boot 2009.08 does it.

Yes, it can go both ways.
> 
> I don't see how the LAN8720 PHY can supply a clock to the SoC. XTAL1 is
> an output only and XTAL2 is only intended to drive a chrystal, and not
> connected anyway. Are we talking about the same board?

The PHY doesn't supply clock on mx28evk, CPU does.
> 
> >> The Ethernet clock is configured properly by
> >> cpu_eth_init in ./arch/arm/cpu/arm926ejs/mx28/mx28.c. But later in the
> >> boot process, board_eth_init in board/denx/m28evk/m28evk.c tries to
> >> configure the Ethernet clock again. Unfortunately that second
> >> 
> >> configuration is just disabling the clock:
> >> 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
> >> 	
> >> 		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
> >> 		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
> >> 
> >> After removing this line, I measured a 25MHz clock, communication with
> >> the PHYs worked and I successfully tftp'ed a kernel from my server.
> > 
> > It's different -- M28EVK and MX28EVK are.
> 
> Yes, I know. I'm working with the MX28EVK, not the M28EVK.
> 
> >> Does you board have an external clock
> >> oscillator for the PHYs?
> > 
> > Yes.
> 
> Aha, so we are talking about different boards.
> 
> >> If not, do you agree with removing this line?
> > 
> > No.
> 
> I'm sorry; I asked the wrong question. What I should have asked was: Do you
> agree with not copying this line to the MX28EVK configuration?

Yea ...

M28EVK: PHY supplies clock to CPU
MX28EVK: CPU supplies clock to PHY

Still, the support is already there.

M