From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sughosh Ganu <urwithsughosh@gmail.com>
Date: Wed, 11 Jan 2012 11:50:00 +0530
Subject: [U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before
 disabling it.
In-Reply-To: <201201102107.58501.marek.vasut@gmail.com>
References: <1326133550-6706-1-git-send-email-urwithsughosh@gmail.com>
	<1326219136-1953-1-git-send-email-urwithsughosh@gmail.com>
	<201201102107.58501.marek.vasut@gmail.com>
Message-ID: <20120111062000.GA12234@Hardy>
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On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > The current implementation invalidates the cache instead of flushing
> > it. This causes problems on platforms where the spl/u-boot is already
> > loaded to the RAM, with caches enabled by a first stage bootloader.
> 
> What platforms are affected?

  It is causing a problem on the hawkboard, where the spl is loaded
  directly to the RAM by a rom bootloader. We did not see this earlier
  since cpu_init_crit was not getting called due to
  CONFIG_SKIP_LOWLEVEL_INIT.

-sughosh