[U-Boot] [PATCH 2/2] i.mx6q: SabreLite: Add SPI NOR support

[Marek Vasut <marek.vasut@gmail.com>]

> From: Eric Nelson <eric.nelson@boundarydevices.com>
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> CC: Jason Liu <jason.hui@linaro.org>
> CC: Stefano Babic <sbabic@denx.de>
> ---
> Note: These two patches are against the recent head of u-boot-imx.git
> including the SabreLite support:
> 
>       5b894e4d00ff94a221f8cc23d54d08b889f54190
>       i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board
> 
>  board/freescale/mx6qsabrelite/imximage.cfg    |    2 +-
>  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   51
> +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h               | 
>  15 +++++++
>  3 files changed, 67 insertions(+), 1 deletions(-)
> 
> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
> b/board/freescale/mx6qsabrelite/imximage.cfg index 83dee6f..c389427 100644
> --- a/board/freescale/mx6qsabrelite/imximage.cfg
> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
> 
>  # set the default clock gate to save power
>  DATA 4 0x020c4068 0x00C03F3F
> -DATA 4 0x020c406c 0x0030FC00
> +DATA 4 0x020c406c 0x0030FC03
>  DATA 4 0x020c4070 0x0FFFC000
>  DATA 4 0x020c4074 0x3FF00000
>  DATA 4 0x020c4078 0x00FFF300
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 4028789..d69adfa
> 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -29,6 +29,10 @@
>  #include <asm/gpio.h>
>  #include <mmc.h>
>  #include <fsl_esdhc.h>
> +#ifdef CONFIG_IMX_ECSPI
> +#include <spi.h>
> +#include <imx_spi.h>
> +#endif
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -40,6 +44,10 @@ DECLARE_GLOBAL_DATA_PTR;
>         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
>         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> 
> +#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
> +       PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
> +       PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
> +
>  int dram_init(void)
>  {
>         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -128,6 +136,46 @@ int board_mmc_init(bd_t *bis)
>  }
>  #endif
> 
> +#ifdef CONFIG_IMX_ECSPI
> +s32 spi_get_cfg(struct imx_spi_dev_t *dev)
> +{
> +	int rval = 0 ;
> +	if (1 == dev->slave.cs) {
> +		dev->base = ECSPI1_BASE_ADDR;
> +		dev->ss = 1 ;

" ;" again.

Also, Do you even need the ecspi thing? Doesn't uboot support some kind of imx 
spi driver already?

M
> +		dev->ss_pol = IMX_SPI_ACTIVE_LOW; /* SPI NOR */
> +		dev->freq = 25000000;
> +		dev->fifo_sz = 64 * 4;
> +		dev->us_delay = 0;
> +	} else {
> +		printf("%s: invalid chip select %d\n", __func__, dev->slave.cs);
> +		rval = -EINVAL ;
> +	}
> +	return rval;
> +}
> +
> +void spi_io_init(struct imx_spi_dev_t *dev, int active)
> +{
> +	if (dev->ss == 1)
> +		gpio_set_value(83, active ? 0 : 1); /* GPIO 3.19 */
> +}
> +
> +iomux_v3_cfg_t ecspi1_pads[] = {
> +	/* SS1 */
> +	MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +};
> +
> +void setup_spi(void)
> +{
> +	gpio_direction_output(83, 1); /* GPIO 3.19 */
> +	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
> +					 ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
>  int board_early_init_f(void)
>  {
>         setup_iomux_uart();
> @@ -140,6 +188,9 @@ int board_init(void)
>         /* address of boot parameters */
>         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> 
> +#ifdef CONFIG_IMX_ECSPI
> +	setup_spi();
> +#endif
>         return 0;
>  }
> 
> diff --git a/include/configs/mx6qsabrelite.h
> b/include/configs/mx6qsabrelite.h index 464f0ec..48db42c 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -44,6 +44,21 @@
>  #define CONFIG_MXC_UART
>  #define CONFIG_MXC_UART_BASE           UART2_BASE
> 
> +#define CONFIG_CMD_SF
> +/*
> + * SPI Configs
> + */
> +#ifdef CONFIG_CMD_SF
> +	#define CONFIG_FSL_SF		1
> +	#define CONFIG_SPI_FLASH       1
> +	#define CONFIG_SPI_FLASH_SST	1
> +	#define CONFIG_SPI_FLASH_CS	1
> +	#define CONFIG_IMX_ECSPI
> +	#define IMX_CSPI_VER_2_3        1
> +
> +	#define MAX_SPI_BYTES		(64 * 4)
> +#endif
> +
>  /* MMC Configs */
>  #define CONFIG_FSL_ESDHC
>  #define CONFIG_FSL_USDHC