[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Sughosh Ganu <urwithsughosh@gmail.com>]

On Fri Jan 13, 2012 at 11:49:57PM +0530, Aneesh V wrote:
> On Friday 13 January 2012 11:08 PM, Sughosh Ganu wrote:

<snip>

> >>
> >>Are you sure, the RBL enables the D-Cache on your board? Nevertheless,
> >>I think, we must disable the D-Cache here with "cleaning" it (as your
> >>patch did) instead only invalidating it, as current code did.
> >
> >   I am not sure, this is just my guess. By default, the caches are
> >   disabled on reset, so the only possible source is the rbl. But I
> >   don't have access to the rbl code to say for sure. Unfortunately i
> >   also don't have JTAG or any other debugger to dig more into
> 
> I will be surprised too if D-cache is enabled by ROM code. But I agree
> that your problem and the solution seems to indicate something like
> that. To be sure can you check the value of CP15 System control
> register on SPL entry? You are already reading it. Can you save it
> somewhere and spit it out later?

  Yes, i can try this out. Spitting it out as is won't be
  straightforward given the limited resources we have with spl(no
  printf). I'll see if i can pass the value to board_init_f, where i
  can check for it, and output some debug message.

> 
> >   this. But yes, like you mention, we must be cleaning the cache
> >   before disabling it, so this fix is correct.
> 
> I think it will be good to add an invalidate of I-cache too. You have
> replaced an invalidate of I & D cache with a flush of only D-cache.

  Ok, will add invalidation of the I cache.

-sughosh