[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Sughosh Ganu <urwithsughosh@gmail.com>]

hi Christian,

On Sat Jan 14, 2012 at 06:20:06PM +0100, Christian Riesch wrote:
> Hi Sughosh,

<snip>

> On Thursday, January 12, 2012, Sughosh Ganu <urwithsughosh@gmail.com> wrote:
> >> 1) The first test was done with the SPL and yes, here the RBL loads
> >> the SPL into SRAM, initializes DDR memory and then copies u-boot.bin
> >> to DDR memory.
> >> 2) The second test was done with TI's UBL. Here, the RBL loads the UBL
> >> into SRAM, the UBL initializes DDR memory and then copies u-boot.bin
> >> to DDR memory.
> >> 3) The third test was done without SPL and without UBL: Here the DDR
> >> memory init is in the AIS, so in fact the RBL does memory
> >> initialization and then RBL loads u-boot.bin to DDR memory. This is
> >> the same case that you have on the hawkboard (only that you have the
> >> OMAP-L138 and NAND flash instead) and it works for me regardless of
> >> your patch.
> >
> >  Yes, the third case is similar to the one used in hawkboard. I'm not
> >  sure as to why it causes a problem on my board, though i'm not sure
> >  if we can compare the two cases, as we have different rbl's. It
> >  could be that the rbl used on hawkboard initialises the caches, as
> >  the caches are off by default on reset.
> >
> >  Here are the values i use in my ini file for ddr init.
> >
> > [EMIF3DDR]
> > PLL1CFG0 = 0x15010001
> > PLL1CFG1 = 0x00000002
> >
> > DDRPHYC1R = 0x00000043
> > SDCR = 0x00134632
> > SDTIMR = 0x26492a09
> > SDTIMR2 = 0x7d13c722
> > SDRCR = 0x00000249
> > CLK2XSRC = 0x00000000

Here it is.
[General]
busWidth=8

BootMode=NAND

crcCheckType=NO_CRC

[PLL0CONFIG]
PLL0CFG0 = 0x00180001
PLL0CFG1 = 0x00000205

[EMIF3DDR]
PLL1CFG0 = 0x15010001
PLL1CFG1 = 0x00000002
DDRPHYC1R = 0x00000043
SDCR = 0x00134632
SDTIMR = 0x26492a09
SDTIMR2 = 0x7d13c722
SDRCR = 0x00000249
CLK2XSRC = 0x00000000
[ARM_EMIF3DDR_PATCHFXN]

-sughosh