From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Thu, 26 Jan 2012 19:32:04 +0100
Subject: [U-Boot] mx28 spl power cpu clock configuration
In-Reply-To: <CAOMZO5BBEdLHiG=a3=3Pa=o3ZCxX9kXCEfxLwEWKGdKGWBhWjQ@mail.gmail.com>
References: <6EA3E0BCC03CC34B89B01BD57ECBC718F26BC7@POBOX.postoffice.danego.net>
	<201201251604.27429.marek.vasut@gmail.com>
	<CAOMZO5BBEdLHiG=a3=3Pa=o3ZCxX9kXCEfxLwEWKGdKGWBhWjQ@mail.gmail.com>
Message-ID: <201201261932.04853.marek.vasut@gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

> Hi Robert,
> 
> On 1/25/12, Marek Vasut <marek.vasut@gmail.com> wrote:
> >> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
> >> gating - before disabling PLL bypass?
> > 
> > This seems reasonable. Fabio, can you comment?
> 
> Could you please post a patch with your proposed change so that we can test
> it?
> 

Hi Fabio,

I bought a really crappy custom board a few days ago (some china-made crap) 
sporting mx287, but apparently I'm hitting similar issue you do here.

When I swap power_init and mem_init though, the board boots fine, othervise it 
hangs.

M