[U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup

[Marek Vasut <marek.vasut@gmail.com>]

> Hi,
> 
> This patch fixes ref_cpu clock setup. This bug leads to a hanging board
> after rebooting from the Kernel, due to failing memory size detection:
> U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
> 
> Freescale i.MX28 family
> I2C:   ready
> DRAM:  0 Bytes
> 
> The cause of the bug is register hw_clkctrl_frac0 being accessed as
> a 32-bit long, whereas the manual specifically states it can be accessed
> as bytes only.
> Applying this patch fixes this problem.

Hi,

you're only writing data to the register, not clearing them. So maybe some bits 
remain set?

Anyway, can you please submit proper patch with git send-email? Thanks!

M

> 
> Signed-off-by: Robert Delien (robert at delien.nl)
> 
> ________________________________________
> From: Marek Vasut [marek.vasut at gmail.com]
> Sent: 26 January 2012 19:32
> To: Fabio Estevam
> Cc: Robert Deli?n; u-boot at lists.denx.de
> Subject: Re: mx28 spl power cpu clock configuration
> 
> > Hi Robert,
> > 
> > On 1/25/12, Marek Vasut <marek.vasut@gmail.com> wrote:
> > >> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
> > >> gating - before disabling PLL bypass?
> > > 
> > > This seems reasonable. Fabio, can you comment?
> > 
> > Could you please post a patch with your proposed change so that we can
> > test it?
> 
> Hi Fabio,
> 
> I bought a really crappy custom board a few days ago (some china-made crap)
> sporting mx287, but apparently I'm hitting similar issue you do here.
> 
> When I swap power_init and mem_init though, the board boots fine, othervise
> it hangs.
> 
> M