[U-Boot] [PATCH 0/3] addition of clocks command for davinci

[U-Boot] [PATCH 0/3] addition of clocks command for davinci

[Manjunath Hadli]

This patch series adds new command - 'clocks' for davinci family
of SOCs. This command prints CPU, DSP core and DDR frequency from
the u-boot prompt. Also, support for printing frequency info during
u-boot initialization is removed as it will delay u-boot coming up.

These patches have undergone a review previously, but since
the tree has moved ahead Christian and Tom asked to resubmit
the patches for review.
(http://www.mail-archive.com/u-boot at lists.denx.de/msg76220.html)

Manjunath Hadli (3):
  davinci: move clock related functions to new file
  davinci: remove macro CONFIG_DISPLAY_CPUINFO
  davinci: add clocks command

 arch/arm/cpu/arm926ejs/davinci/Makefile  |    2 +-
 arch/arm/cpu/arm926ejs/davinci/cpu.c     |  208 ---------------------------
 arch/arm/cpu/arm926ejs/davinci/speed.c   |  230 ++++++++++++++++++++++++++++++
 include/configs/cam_enc_4xx.h            |    1 -
 include/configs/davinci_dm355evm.h       |    1 -
 include/configs/davinci_dm355leopard.h   |    1 -
 include/configs/davinci_dm6467Tevm.h     |    1 -
 include/configs/davinci_dm6467evm.h      |    1 -
 include/configs/davinci_dvevm.h          |    1 -
 include/configs/davinci_schmoogie.h      |    1 -
 include/configs/davinci_sffsdr.h         |    1 -
 include/configs/davinci_sonata.h         |    1 -
 include/configs/enbw_cmc.h               |    1 -
 nand_spl/board/davinci/da8xxevm/Makefile |    6 +
 14 files changed, 237 insertions(+), 219 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c

[U-Boot] [PATCH 1/3] davinci: move clock related functions to new file

[Manjunath Hadli]

Move the clock related function from cpu.c to new file
speed.c. Eliminate volatile keyword usage which made no
justification and also to keep checkpatch.pl happy. Replace
REG instructions by readl.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/Makefile  |    2 +-
 arch/arm/cpu/arm926ejs/davinci/cpu.c     |  208 ---------------------------
 arch/arm/cpu/arm926ejs/davinci/speed.c   |  230 ++++++++++++++++++++++++++++++
 nand_spl/board/davinci/da8xxevm/Makefile |    6 +
 4 files changed, 237 insertions(+), 209 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c

diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index da7efac..81540fd 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS-y				+= cpu.o misc.o timer.o psc.o pinmux.o
+COBJS-y				+= cpu.o misc.o timer.o psc.o pinmux.o speed.o
 COBJS-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
 COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 9ea9785..c2f72d6 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -22,214 +22,6 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL	0x100
-#define PLLC_PLLM	0x110
-#define PLLC_PREDIV	0x114
-#define PLLC_PLLDIV1	0x118
-#define PLLC_PLLDIV2	0x11c
-#define PLLC_PLLDIV3	0x120
-#define PLLC_POSTDIV	0x128
-#define PLLC_BPDIV	0x12c
-#define PLLC_PLLDIV4	0x160
-#define PLLC_PLLDIV5	0x164
-#define PLLC_PLLDIV6	0x168
-#define PLLC_PLLDIV7	0x16c
-#define PLLC_PLLDIV8	0x170
-#define PLLC_PLLDIV9	0x174
-
-#define BIT(x)		(1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
-	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
-	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
-	int pre_div;
-	int pllm;
-	int post_div;
-	int pll_out;
-	unsigned int pll_base;
-
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
-
-	if (id == DAVINCI_AUXCLK_CLKID)
-		goto out;
-
-	if ((id >> 16) == 1)
-		pll_base = (unsigned int)davinci_pllc1_regs;
-	else
-		pll_base = (unsigned int)davinci_pllc0_regs;
-
-	id &= 0xFFFF;
-
-	/*
-	 * Lets keep this simple. Combining operations can result in
-	 * unexpected approximations
-	 */
-	pre_div = (readl(pll_base + PLLC_PREDIV) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-	pllm = readl(pll_base + PLLC_PLLM) + 1;
-
-	pll_out /= pre_div;
-	pll_out *= pllm;
-
-	if (id == DAVINCI_PLLM_CLKID)
-		goto out;
-
-	post_div = (readl(pll_base + PLLC_POSTDIV) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-
-	pll_out /= post_div;
-
-	if (id == DAVINCI_PLLC_CLKID)
-		goto out;
-
-	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
-	return pll_out;
-}
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-	printf("Cores: ARM %d MHz",
-			clk_get(DAVINCI_ARM_CLKID) / 1000000);
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			clk_get(0x10001) / 1000000);
-	return 0;
-}
-#endif
-#else /* CONFIG_SOC_DA8XX */
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
-	u32	div;
-
-	div = REG(pllbase + offset);
-	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	/* this register read seems to fail on pll0 */
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return 8;
-	else
-		return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
-	return pll_div(pllbase, PLLC_PREDIV);
-#endif
-	return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
-	return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return pll_div(pllbase, PLLC_POSTDIV);
-#endif
-	return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
-	volatile void	*pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
-	unsigned	base = CFG_REFCLK_FREQ / 1000;
-#else
-	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
-	/* the PLL might be bypassed */
-	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
-		base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
-		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
-		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
-		base /= pll_postdiv(pllbase);
-	}
-	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-int print_cpuinfo(void)
-{
-	/* REVISIT fetch and display CPU ID and revision information
-	 * too ... that will matter as more revisions appear.
-	 */
-#if defined(CONFIG_SOC_DM365)
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
-#else
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-#endif
-
-#ifdef DSP_PLLDIV
-	printf(", DSP %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
-				/ 2);
-#else
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
-#endif
-	return 0;
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
-#endif /* !CONFIG_SOC_DA8XX */
 
 /*
  * Initializes on-chip ethernet controllers.
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
new file mode 100644
index 0000000..5285142
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2012 Texas Instruments.
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL	0x100
+#define PLLC_PLLM	0x110
+#define PLLC_PREDIV	0x114
+#define PLLC_PLLDIV1	0x118
+#define PLLC_PLLDIV2	0x11c
+#define PLLC_PLLDIV3	0x120
+#define PLLC_POSTDIV	0x128
+#define PLLC_BPDIV	0x12c
+#define PLLC_PLLDIV4	0x160
+#define PLLC_PLLDIV5	0x164
+#define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV7	0x16c
+#define PLLC_PLLDIV8	0x170
+#define PLLC_PLLDIV9	0x174
+
+#define BIT(x)		(1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DA8XX
+unsigned int sysdiv[9] = {
+	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+	int pre_div;
+	int pllm;
+	int post_div;
+	int pll_out;
+	unsigned int pll_base;
+
+	pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+	if (id == DAVINCI_AUXCLK_CLKID)
+		goto out;
+
+	if ((id >> 16) == 1)
+		pll_base = (unsigned int)davinci_pllc1_regs;
+	else
+		pll_base = (unsigned int)davinci_pllc0_regs;
+
+	id &= 0xFFFF;
+
+	/*
+	 * Lets keep this simple. Combining operations can result in
+	 * unexpected approximations
+	 */
+	pre_div = (readl(pll_base + PLLC_PREDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+	pllm = readl(pll_base + PLLC_PLLM) + 1;
+
+	pll_out /= pre_div;
+	pll_out *= pllm;
+
+	if (id == DAVINCI_PLLM_CLKID)
+		goto out;
+
+	post_div = (readl(pll_base + PLLC_POSTDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+	pll_out /= post_div;
+
+	if (id == DAVINCI_PLLC_CLKID)
+		goto out;
+
+	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+	return pll_out;
+}
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	printf("Cores: ARM %d MHz",
+			clk_get(DAVINCI_ARM_CLKID) / 1000000);
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+			clk_get(0x10001) / 1000000);
+	return 0;
+}
+#endif
+#else /* CONFIG_SOC_DA8XX */
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+
+static unsigned pll_div(unsigned pllbase, unsigned offset)
+{
+	u32	div;
+
+	div = readl(pllbase + offset);
+	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(unsigned pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	/* this register read seems to fail on pll0 */
+	if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
+		return 8;
+	else
+		return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_PREDIV);
+#endif
+	return 1;
+}
+
+static inline unsigned pll_postdiv(unsigned pllbase)
+{
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+	if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
+		return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+	return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+#ifdef CONFIG_SOC_DM646X
+	unsigned	base = CFG_REFCLK_FREQ / 1000;
+#else
+	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
+
+	/* the PLL might be bypassed */
+	if (readl(pll_addr + PLLC_PLLCTL) & BIT(0)) {
+		base /= pll_prediv(pll_addr);
+#if defined(CONFIG_SOC_DM365)
+		base *=  2 * (readl(pll_addr + PLLC_PLLM) & 0x0ff);
+#else
+		base *= 1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff);
+#endif
+		base /= pll_postdiv(pll_addr);
+	}
+	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
+}
+
+int print_cpuinfo(void)
+{
+	/* REVISIT fetch and display CPU ID and revision information
+	 * too ... that will matter as more revisions appear.
+	 */
+#if defined(CONFIG_SOC_DM365)
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
+
+#ifdef DSP_PLLDIV
+	printf(", DSP %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
+#endif
+
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+				/ 2);
+#else
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
+				/ 2);
+#endif
+	return 0;
+}
+
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
+#endif /* CONFIG_DISPLAY_CPUINFO */
+#endif /* !CONFIG_SOC_DA8XX */
diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile
index 7746e41..cfbe319 100644
--- a/nand_spl/board/davinci/da8xxevm/Makefile
+++ b/nand_spl/board/davinci/da8xxevm/Makefile
@@ -41,6 +41,7 @@ SOBJS	= _divsi3.o \
 	start.o
 
 COBJS	= cpu.o \
+	speed.o \
 	davinci_nand.o \
 	pinmux.o \
 	da850_pinmux.o \
@@ -126,6 +127,11 @@ $(obj)cpu.c:
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/cpu.c $@
 
+# from SoC directory
+$(obj)speed.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/speed.c $@
+
 $(obj)misc.c:
 	@rm -f $@
 	ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/misc.c $@
-- 
1.6.2.4

[U-Boot] [PATCH 2/3] davinci: remove macro CONFIG_DISPLAY_CPUINFO

[Manjunath Hadli]

remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'clocks' command. Also avoid building of print_cpuinfo() function
for SPL framework.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c |    5 +----
 include/configs/cam_enc_4xx.h          |    1 -
 include/configs/davinci_dm355evm.h     |    1 -
 include/configs/davinci_dm355leopard.h |    1 -
 include/configs/davinci_dm6467Tevm.h   |    1 -
 include/configs/davinci_dm6467evm.h    |    1 -
 include/configs/davinci_dvevm.h        |    1 -
 include/configs/davinci_schmoogie.h    |    1 -
 include/configs/davinci_sffsdr.h       |    1 -
 include/configs/davinci_sonata.h       |    1 -
 include/configs/enbw_cmc.h             |    1 -
 11 files changed, 1 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 5285142..156419b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -114,7 +114,7 @@ int clk_get(enum davinci_clk_ids id)
 out:
 	return pll_out;
 }
-#ifdef CONFIG_DISPLAY_CPUINFO
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
 int print_cpuinfo(void)
 {
 	printf("Cores: ARM %d MHz",
@@ -127,8 +127,6 @@ int print_cpuinfo(void)
 #endif
 #else /* CONFIG_SOC_DA8XX */
 
-#ifdef CONFIG_DISPLAY_CPUINFO
-
 static unsigned pll_div(unsigned pllbase, unsigned offset)
 {
 	u32	div;
@@ -226,5 +224,4 @@ unsigned int davinci_clk_get(unsigned int div)
 	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
 }
 #endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
 #endif /* !CONFIG_SOC_DA8XX */
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index a21d448..419cfd4 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -257,7 +257,6 @@
 #define CONFIG_POST	CONFIG_SYS_POST_MEMORY
 #define _POST_WORD_ADDR	0x0
 
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index ddf673c..8578730 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -26,7 +26,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index dfa0a00..eaff66e 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -25,7 +25,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h
index b3a4e44..f7c994e 100644
--- a/include/configs/davinci_dm6467Tevm.h
+++ b/include/configs/davinci_dm6467Tevm.h
@@ -23,7 +23,6 @@
 /* Spectrum Digital TMS320DM6467T EVM board */
 #define DAVINCI_DM6467EVM
 #define DAVINCI_DM6467TEVM
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_NAND_SMALLPAGE
 
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index c9a0cd1..ddfd3ed 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -22,7 +22,6 @@
 
 /* Spectrum Digital TMS320DM6467 EVM board */
 #define DAVINCI_DM6467EVM
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_NAND_SMALLPAGE
 
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index c052517..a2aa3c3 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -51,7 +51,6 @@
 #define DV_EVM
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index f4ddbea..e0a8ee9 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -26,7 +26,6 @@
 #define SCHMOOGIE
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
 #define MACH_TYPE_SCHMOOGIE 1255
 #define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
 
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 0c65391..a2da65a 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
-#define CONFIG_DISPLAY_CPUINFO
 /* SoC Configuration */
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index fc4d8ec..db47966 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -51,7 +51,6 @@
 #define SONATA_BOARD
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NOR
-#define CONFIG_DISPLAY_CPUINFO
 #define MACH_TYPE_SONATA 1254
 #define CONFIG_MACH_TYPE MACH_TYPE_SONATA
 /*===================*/
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index c427dc7..1cbc5cc 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -50,7 +50,6 @@
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DA8XX_GPIO
 #define CONFIG_HOSTNAME		enbw_cmc
-#define CONFIG_DISPLAY_CPUINFO
 
 #define MACH_TYPE_ENBW_CMC	3585
 #define CONFIG_MACH_TYPE	MACH_TYPE_ENBW_CMC
-- 
1.6.2.4

[U-Boot] [PATCH 3/3] davinci: add clocks command

[Manjunath Hadli]

Add 'clocks' command to print various frequencies such as ARM
frequency, DSP core frequency and DDR frequency. Remove
print_cpuinfo() function as it is no longer required.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c |   73 ++++++++++++++++---------------
 1 files changed, 38 insertions(+), 35 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 156419b..eb969e5 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -21,6 +21,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
@@ -114,17 +115,6 @@ int clk_get(enum davinci_clk_ids id)
 out:
 	return pll_out;
 }
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
-int print_cpuinfo(void)
-{
-	printf("Cores: ARM %d MHz",
-			clk_get(DAVINCI_ARM_CLKID) / 1000000);
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			clk_get(0x10001) / 1000000);
-	return 0;
-}
-#endif
 #else /* CONFIG_SOC_DA8XX */
 
 static unsigned pll_div(unsigned pllbase, unsigned offset)
@@ -181,47 +171,60 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
 }
 
-int print_cpuinfo(void)
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
+#endif /* !CONFIG_SOC_DA8XX */
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
+int showclocks(cmd_tbl_t *cmdtp,
+		int flag, int argc, char * const argv[])
 {
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
-#if defined(CONFIG_SOC_DM365)
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+
+	puts("Clock configuration:\n");
+#if defined(CONFIG_SOC_DA8XX)
+	printf("Cores: ARM %d MHz", clk_get(DAVINCI_ARM_CLKID) / 1000000);
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+			clk_get(0x10001) / 1000000);
 #else
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+	unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+
+#if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
 #endif
+	printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, ARM_PLLDIV));
 
 #ifdef DSP_PLLDIV
 	printf(", DSP %d MHz",
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
 #endif
 
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+ #if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL0_BASE;
+ #endif
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
-				/ 2);
-#else
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
+			pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2);
 #endif
 	return 0;
 }
 
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
+U_BOOT_CMD(clocks, 1, 0, showclocks,
+	"display clocks", "");
 
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
 #endif
-#endif /* !CONFIG_SOC_DA8XX */
-- 
1.6.2.4

[U-Boot] [PATCH 3/3] davinci: add clocks command

[Tom Rini]

On Thu, Feb 2, 2012 at 6:53 AM, Manjunath Hadli <manjunath.hadli@ti.com> wrote:
> Add 'clocks' command to print various frequencies such as ARM
> frequency, DSP core frequency and DDR frequency. Remove
> print_cpuinfo() function as it is no longer required.
>
> Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
> Cc: Tom Rini <trini@ti.com>

NAK.  The feedback from the last time you submitted this was to extend
the functionality of 'bdinfo' to be able to include this.  See
http://patchwork.ozlabs.org/patch/120105/

-- 
Tom

[U-Boot] [PATCH 1/3] davinci: move clock related functions to new file

[Sughosh Ganu]

hi Manjunath,

On Thu Feb 02, 2012 at 07:23:20PM +0530, Manjunath Hadli wrote:
> Move the clock related function from cpu.c to new file
> speed.c. Eliminate volatile keyword usage which made no
> justification and also to keep checkpatch.pl happy. Replace
> REG instructions by readl.
> 
> Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
> Cc: Tom Rini <trini@ti.com>
> ---


>  nand_spl/board/davinci/da8xxevm/Makefile |    6 +

   You might want to check the patch "Changes to move hawkboard to the
   new spl infrastructure". This patch removes the above file, and
   moves the hawkboard to the new spl infrastructure -- the above
   change would not be needed.

-sughosh

[U-Boot] [PATCH 3/3] davinci: add clocks command

[Hadli, Manjunath]

Tom,

On Thu, Feb 02, 2012 at 22:18:09, Tom Rini wrote:
> On Thu, Feb 2, 2012 at 6:53 AM, Manjunath Hadli <manjunath.hadli@ti.com> wrote:
> > Add 'clocks' command to print various frequencies such as ARM 
> > frequency, DSP core frequency and DDR frequency. Remove
> > print_cpuinfo() function as it is no longer required.
> >
> > Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
> > Cc: Tom Rini <trini@ti.com>
> 
> NAK.  The feedback from the last time you submitted this was to extend the functionality of 'bdinfo' to be able to include this.  See http://patchwork.ozlabs.org/patch/120105/
Agreed. I will implement this functionality as part 'bdinfo' command and resubmit the patches.

Regards,
--Manju
> 
> --
> Tom
>