[U-Boot] [PATCH 0/4] i.MX28: Small correction to pin configuration

[U-Boot] [PATCH 0/4] i.MX28: Small correction to pin configuration

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This patch makes a small correction to the mx28evk board pin
configuration.

1. The Debug UART (DUART) SPIO pins should be operating in the 3v3
domain, not the 1v8 domain, because the connected MX3222 level-
shifter operates in the 3v3 domain too.

2. The SSP0 card detect pin doesn't require a drive strength
configuration because it's an input. Configuring it as all other
SSP0 pins will do here.
A SSP0 clock signal drive strength of 12mA is much too loud. The FSL
supplied U-Boot uses the same drive strength for the clock as it does
for all ohter SSP0 signals.
The Write-protect input is configured the same, yet more explicitly
specified.

3. Pin configuration for SSP1 has been added for MMC1. Because the
use of MMC1 is mutually exclusive with the use of NAND flash, this
is only active when NAND flash is not configured in.

4. Pin configuration for NAND flash has been added.

Robert Delien (4):
  Debug UART pins configured to 3v3, instead of 1v8
  Correction to SSP0 drive strengths
  SSP1 pins configured for MMC1
  Added NAND flash pin configuration

 board/freescale/mx28evk/iomux.c |   71 ++++++++++++++++++++++++++++++++------
 1 files changed, 59 insertions(+), 12 deletions(-)

[U-Boot] [PATCH 1/4] Debug UART pins configured to 3v3, instead of 1v8

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>


Signed-off-by: Robert Delien <robert@delien.nl>
---
 board/freescale/mx28evk/iomux.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 396761b..d724d2f 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -31,9 +31,9 @@
 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
 
 const iomux_cfg_t iomux_setup[] = {
-	/* DUART */
-	MX28_PAD_PWM0__DUART_RX,
-	MX28_PAD_PWM1__DUART_TX,
+	/* Debug UART (DUART) */
+	MX28_PAD_PWM0__DUART_RX | MXS_PAD_3V3,
+	MX28_PAD_PWM1__DUART_TX | MXS_PAD_3V3,
 
 	/* MMC0 */
 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
-- 
1.7.0.4

[U-Boot] [PATCH 2/4] Correction to SSP0 drive strengths

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>


Signed-off-by: Robert Delien <robert@delien.nl>
---
 board/freescale/mx28evk/iomux.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index d724d2f..178bde2 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -35,7 +35,7 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_PWM0__DUART_RX | MXS_PAD_3V3,
 	MX28_PAD_PWM1__DUART_TX | MXS_PAD_3V3,
 
-	/* MMC0 */
+	/* Right-hand side MMC slot (MMC0) */
 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
@@ -45,15 +45,13 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
 	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* write protect */
-	MX28_PAD_SSP1_SCK__GPIO_2_12,
+	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+	/* MMC0 Write-protect */
+	MX28_PAD_SSP1_SCK__GPIO_2_12 | MXS_PAD_3V3 | MXS_PAD_PULLUP,
 	/* MMC0 slot power enable */
 	MX28_PAD_PWM3__GPIO_3_28 |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+		MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
 
 	/* FEC0 */
 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
-- 
1.7.0.4

[U-Boot] [PATCH 3/4] SSP1 pins configured for MMC1

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>


Signed-off-by: Robert Delien <robert@delien.nl>
---
 board/freescale/mx28evk/iomux.c |   27 ++++++++++++++++++++++++++-
 1 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 178bde2..d6f9d0a 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -26,9 +26,9 @@
 #include <asm/arch/sys_proto.h>
 
 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* Debug UART (DUART) */
@@ -53,6 +53,31 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_PWM3__GPIO_3_28 |
 		MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
 
+#ifndef CONFIG_CMD_NAND
+	/* Left-hand side MMC slot (MMC1) */
+	MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D04__SSP1_D4 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D05__SSP1_D5 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D06__SSP1_D6 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_D07__SSP1_D7 | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | MUX_CONFIG_SSP1,
+	MX28_PAD_GPMI_WRN__SSP1_SCK | MUX_CONFIG_SSP1,
+	/* MMC1 Write-protect */
+	MX28_PAD_GPMI_RESETN__GPIO_0_28 | MXS_PAD_3V3 | MXS_PAD_PULLUP,
+	/* MMC1 slot power enable */
+	MX28_PAD_PWM4__GPIO_3_29 |
+		MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
+	/* Not used for MMC1 */
+	MX28_PAD_GPMI_RDN__GPIO_0_24 | MXS_PAD_3V3,
+	MX28_PAD_GPMI_CLE__GPIO_0_27 | MXS_PAD_3V3,
+	MX28_PAD_GPMI_ALE__GPIO_0_26 | MXS_PAD_3V3,
+	MX28_PAD_GPMI_CE1N__GPIO_0_17 | MXS_PAD_3V3,
+	MX28_PAD_GPMI_CE0N__GPIO_0_16 | MXS_PAD_3V3,
+#endif /* nCONFIG_CMD_NAND */
 	/* FEC0 */
 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
-- 
1.7.0.4

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>


Signed-off-by: Robert Delien <robert@delien.nl>
---
 board/freescale/mx28evk/iomux.c |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index d6f9d0a..781f36d 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -29,6 +29,7 @@
 #define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_NAND	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* Debug UART (DUART) */
@@ -77,6 +78,29 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_GPMI_ALE__GPIO_0_26 | MXS_PAD_3V3,
 	MX28_PAD_GPMI_CE1N__GPIO_0_17 | MXS_PAD_3V3,
 	MX28_PAD_GPMI_CE0N__GPIO_0_16 | MXS_PAD_3V3,
+#else
+	/* On-board NAND flash ZIF-socket  */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP,
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_RDY1__GPMI_READY1 | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_NAND,
+	MX28_PAD_GPMI_CE1N__GPMI_CE1N | MUX_CONFIG_NAND,
+	/* NAND Write-protect */
+	MX28_PAD_GPMI_RESETN__GPIO_0_28 | MXS_PAD_3V3,
+	/* Not used for NAND flash */
+	MX28_PAD_PWM4__GPIO_3_29 | MXS_PAD_3V3,
 #endif /* nCONFIG_CMD_NAND */
 	/* FEC0 */
 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
-- 
1.7.0.4

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Marek Vasut]

> From: Robert Delien <robert@delien.nl>

Description of the patches won't hurt ;-)

Otherwise, these patches are Fabios ... so he'll ack/nak them

M
> 
> 
> Signed-off-by: Robert Delien <robert@delien.nl>
> ---
>  board/freescale/mx28evk/iomux.c |   24 ++++++++++++++++++++++++
>  1 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/board/freescale/mx28evk/iomux.c
> b/board/freescale/mx28evk/iomux.c index d6f9d0a..781f36d 100644
> --- a/board/freescale/mx28evk/iomux.c
> +++ b/board/freescale/mx28evk/iomux.c
> @@ -29,6 +29,7 @@
>  #define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
>  #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
>  #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
> +#define	MUX_CONFIG_NAND	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
> 
>  const iomux_cfg_t iomux_setup[] = {
>  	/* Debug UART (DUART) */
> @@ -77,6 +78,29 @@ const iomux_cfg_t iomux_setup[] = {
>  	MX28_PAD_GPMI_ALE__GPIO_0_26 | MXS_PAD_3V3,
>  	MX28_PAD_GPMI_CE1N__GPIO_0_17 | MXS_PAD_3V3,
>  	MX28_PAD_GPMI_CE0N__GPIO_0_16 | MXS_PAD_3V3,
> +#else
> +	/* On-board NAND flash ZIF-socket  */
> +	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDN__GPMI_RDN |
> +		MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP,
> +	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDY1__GPMI_READY1 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CE1N__GPMI_CE1N | MUX_CONFIG_NAND,
> +	/* NAND Write-protect */
> +	MX28_PAD_GPMI_RESETN__GPIO_0_28 | MXS_PAD_3V3,
> +	/* Not used for NAND flash */
> +	MX28_PAD_PWM4__GPIO_3_29 | MXS_PAD_3V3,
>  #endif /* nCONFIG_CMD_NAND */
>  	/* FEC0 */
>  	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Matthias Fuchs]

Do you plan to post a patch to enable NAND on the EVK as well?
That shouldn't be a big deal.

Matthias

On 07.02.2012 17:52, robert at delien.nl wrote:
> From: Robert Delien <robert@delien.nl>
> 
> 
> Signed-off-by: Robert Delien <robert@delien.nl>
> ---
>  board/freescale/mx28evk/iomux.c |   24 ++++++++++++++++++++++++
>  1 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
> index d6f9d0a..781f36d 100644
> --- a/board/freescale/mx28evk/iomux.c
> +++ b/board/freescale/mx28evk/iomux.c
> @@ -29,6 +29,7 @@
>  #define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
>  #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
>  #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
> +#define	MUX_CONFIG_NAND	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
>  
>  const iomux_cfg_t iomux_setup[] = {
>  	/* Debug UART (DUART) */
> @@ -77,6 +78,29 @@ const iomux_cfg_t iomux_setup[] = {
>  	MX28_PAD_GPMI_ALE__GPIO_0_26 | MXS_PAD_3V3,
>  	MX28_PAD_GPMI_CE1N__GPIO_0_17 | MXS_PAD_3V3,
>  	MX28_PAD_GPMI_CE0N__GPIO_0_16 | MXS_PAD_3V3,
> +#else
> +	/* On-board NAND flash ZIF-socket  */
> +	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDN__GPMI_RDN |
> +		MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP,
> +	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_RDY1__GPMI_READY1 | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_NAND,
> +	MX28_PAD_GPMI_CE1N__GPMI_CE1N | MUX_CONFIG_NAND,
> +	/* NAND Write-protect */
> +	MX28_PAD_GPMI_RESETN__GPIO_0_28 | MXS_PAD_3V3,
> +	/* Not used for NAND flash */
> +	MX28_PAD_PWM4__GPIO_3_29 | MXS_PAD_3V3,
>  #endif /* nCONFIG_CMD_NAND */
>  	/* FEC0 */
>  	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Robert Deliën]

> Do you plan to post a patch to enable NAND on the EVK as well?

Yes, I do. It's all tested and working in my workspace. But the first
samples of our own board have arrived a couple of days ago and I'm
currently in the process of bringing it up and that has priority over
everything else, hence the silence.

I've got I2C, UARTs both MMC slots and USB working as well.

> That shouldn't be a big deal.

It was of 5 minute job, 1 of which was compile-time. Unfortunately
making a patch and reworking all comments is not.

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Matthias Fuchs]

On 10.02.2012 13:42, Robert Deli?n wrote:
>> Do you plan to post a patch to enable NAND on the EVK as well?
> 
> Yes, I do. It's all tested and working in my workspace. But the first
> samples of our own board have arrived a couple of days ago and I'm
> currently in the process of bringing it up and that has priority over
> everything else, hence the silence.
> 
> I've got I2C, UARTs both MMC slots and USB working as well.
> 
>> That shouldn't be a big deal.
> 
> It was of 5 minute job, 1 of which was compile-time. Unfortunately
> making a patch and reworking all comments is not.
So I can lean back ...

Matthias

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Robert Deliën]

> So I can lean back ...

I can even send you a patch of what I have, if that helps you out...

[U-Boot] [PATCH 4/4] Added NAND flash pin configuration

[Robert Deliën]

> Do you plan to post a patch to enable NAND on the EVK as well?

No, I'm afraid not anymore.

> That shouldn't be a big deal.

The patch isn't, but getting it accepted is.