[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This set of patches fixes ref_cpu clock setup.

Robert Delien (4):
  Renamed mx28_register to mx28_register_32 to prepare for
    mx28_register_8
  Introducing 8-bit wide register, mx28_register_8
  Fix erroneous 32-bit access to hw_clkctrl_frac0 and
    hw_clkctrl_frac1 registers
  Preventing needless switching on and off PLL bypass mode,
    allowing allow single-stepping through the SPL

 arch/arm/cpu/arm926ejs/mx28/clock.c           |    4 +-
 arch/arm/cpu/arm926ejs/mx28/iomux.c           |    6 +-
 arch/arm/cpu/arm926ejs/mx28/mx28.c            |    6 +-
 arch/arm/include/asm/arch-mx28/regs-apbh.h    |  254 ++++++++++++------------
 arch/arm/include/asm/arch-mx28/regs-bch.h     |   42 ++--
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   58 +++---
 arch/arm/include/asm/arch-mx28/regs-common.h  |   12 +-
 arch/arm/include/asm/arch-mx28/regs-gpmi.h    |   26 ++--
 arch/arm/include/asm/arch-mx28/regs-i2c.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ocotp.h   |   86 ++++----
 arch/arm/include/asm/arch-mx28/regs-pinctrl.h |  168 ++++++++--------
 arch/arm/include/asm/arch-mx28/regs-power.h   |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-rtc.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ssp.h     |   40 ++--
 arch/arm/include/asm/arch-mx28/regs-timrot.h  |   38 ++--
 arch/arm/include/asm/arch-mx28/regs-usbphy.h  |   20 +-
 arch/arm/include/asm/arch-mx28/sys_proto.h    |   10 +-
 drivers/gpio/mxs_gpio.c                       |   16 +-
 drivers/usb/host/ehci-mxs.c                   |    8 +-
 19 files changed, 441 insertions(+), 437 deletions(-)

[U-Boot] [PATCH 1/4 v4] Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.

Signed-off-by: Robert Delien <robert@delien.nl>
---
 arch/arm/cpu/arm926ejs/mx28/clock.c           |    4 +-
 arch/arm/cpu/arm926ejs/mx28/iomux.c           |    6 +-
 arch/arm/cpu/arm926ejs/mx28/mx28.c            |    6 +-
 arch/arm/include/asm/arch-mx28/regs-apbh.h    |  254 ++++++++++++------------
 arch/arm/include/asm/arch-mx28/regs-bch.h     |   42 ++--
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   58 +++---
 arch/arm/include/asm/arch-mx28/regs-common.h  |   12 +-
 arch/arm/include/asm/arch-mx28/regs-gpmi.h    |   26 ++--
 arch/arm/include/asm/arch-mx28/regs-i2c.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ocotp.h   |   86 ++++----
 arch/arm/include/asm/arch-mx28/regs-pinctrl.h |  168 ++++++++--------
 arch/arm/include/asm/arch-mx28/regs-power.h   |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-rtc.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ssp.h     |   40 ++--
 arch/arm/include/asm/arch-mx28/regs-timrot.h  |   38 ++--
 arch/arm/include/asm/arch-mx28/regs-usbphy.h  |   20 +-
 arch/arm/include/asm/arch-mx28/sys_proto.h    |   10 +-
 drivers/gpio/mxs_gpio.c                       |   16 +-
 drivers/usb/host/ehci-mxs.c                   |    8 +-
 19 files changed, 441 insertions(+), 437 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c
index f698506..9d3a018 100644
--- a/arch/arm/cpu/arm926ejs/mx28/clock.c
+++ b/arch/arm/cpu/arm926ejs/mx28/clock.c
@@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
 	while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
@@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 		return XTAL_FREQ_KHZ;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
 
diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c
index 9ea411f..12916b6 100644
--- a/arch/arm/cpu/arm926ejs/mx28/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mx28/iomux.c
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 {
 	u32 reg, ofs, bp, bm;
 	void *iomux_base = (void *)MXS_PINCTRL_BASE;
-	struct mx28_register *mxs_reg;
+	struct mx28_register_32 *mxs_reg;
 
 	/* muxsel */
 	ofs = 0x100;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 	/* vol */
 	if (PAD_VOL_VALID(pad)) {
 		bp = PAD_PIN(pad) % 8 * 4 + 2;
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_VOL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 		ofs = PULL_OFFSET;
 		ofs += PAD_BANK(pad) * 0x10;
 		bp = PAD_PIN(pad);
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_PULL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index 683777f..0e69193 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -63,7 +63,7 @@ void reset_cpu(ulong ignored)
 		;
 }
 
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)
@@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)
@@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_reset_block(struct mx28_register *reg)
+int mx28_reset_block(struct mx28_register_32 *reg)
 {
 	/* Clear SFTRST */
 	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h
index a7fa1ec..91d7bc8 100644
--- a/arch/arm/include/asm/arch-mx28/regs-apbh.h
+++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h
@@ -30,142 +30,142 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_apbh_regs {
-	mx28_reg(hw_apbh_ctrl0)
-	mx28_reg(hw_apbh_ctrl1)
-	mx28_reg(hw_apbh_ctrl2)
-	mx28_reg(hw_apbh_channel_ctrl)
-	mx28_reg(hw_apbh_devsel)
-	mx28_reg(hw_apbh_dma_burst_size)
-	mx28_reg(hw_apbh_debug)
+	mx28_reg_32(hw_apbh_ctrl0)
+	mx28_reg_32(hw_apbh_ctrl1)
+	mx28_reg_32(hw_apbh_ctrl2)
+	mx28_reg_32(hw_apbh_channel_ctrl)
+	mx28_reg_32(hw_apbh_devsel)
+	mx28_reg_32(hw_apbh_dma_burst_size)
+	mx28_reg_32(hw_apbh_debug)
 
 	uint32_t	reserved[36];
 
 	union {
 	struct {
-		mx28_reg(hw_apbh_ch_curcmdar)
-		mx28_reg(hw_apbh_ch_nxtcmdar)
-		mx28_reg(hw_apbh_ch_cmd)
-		mx28_reg(hw_apbh_ch_bar)
-		mx28_reg(hw_apbh_ch_sema)
-		mx28_reg(hw_apbh_ch_debug1)
-		mx28_reg(hw_apbh_ch_debug2)
+		mx28_reg_32(hw_apbh_ch_curcmdar)
+		mx28_reg_32(hw_apbh_ch_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch_cmd)
+		mx28_reg_32(hw_apbh_ch_bar)
+		mx28_reg_32(hw_apbh_ch_sema)
+		mx28_reg_32(hw_apbh_ch_debug1)
+		mx28_reg_32(hw_apbh_ch_debug2)
 	} ch[16];
 	struct {
-		mx28_reg(hw_apbh_ch0_curcmdar)
-		mx28_reg(hw_apbh_ch0_nxtcmdar)
-		mx28_reg(hw_apbh_ch0_cmd)
-		mx28_reg(hw_apbh_ch0_bar)
-		mx28_reg(hw_apbh_ch0_sema)
-		mx28_reg(hw_apbh_ch0_debug1)
-		mx28_reg(hw_apbh_ch0_debug2)
-		mx28_reg(hw_apbh_ch1_curcmdar)
-		mx28_reg(hw_apbh_ch1_nxtcmdar)
-		mx28_reg(hw_apbh_ch1_cmd)
-		mx28_reg(hw_apbh_ch1_bar)
-		mx28_reg(hw_apbh_ch1_sema)
-		mx28_reg(hw_apbh_ch1_debug1)
-		mx28_reg(hw_apbh_ch1_debug2)
-		mx28_reg(hw_apbh_ch2_curcmdar)
-		mx28_reg(hw_apbh_ch2_nxtcmdar)
-		mx28_reg(hw_apbh_ch2_cmd)
-		mx28_reg(hw_apbh_ch2_bar)
-		mx28_reg(hw_apbh_ch2_sema)
-		mx28_reg(hw_apbh_ch2_debug1)
-		mx28_reg(hw_apbh_ch2_debug2)
-		mx28_reg(hw_apbh_ch3_curcmdar)
-		mx28_reg(hw_apbh_ch3_nxtcmdar)
-		mx28_reg(hw_apbh_ch3_cmd)
-		mx28_reg(hw_apbh_ch3_bar)
-		mx28_reg(hw_apbh_ch3_sema)
-		mx28_reg(hw_apbh_ch3_debug1)
-		mx28_reg(hw_apbh_ch3_debug2)
-		mx28_reg(hw_apbh_ch4_curcmdar)
-		mx28_reg(hw_apbh_ch4_nxtcmdar)
-		mx28_reg(hw_apbh_ch4_cmd)
-		mx28_reg(hw_apbh_ch4_bar)
-		mx28_reg(hw_apbh_ch4_sema)
-		mx28_reg(hw_apbh_ch4_debug1)
-		mx28_reg(hw_apbh_ch4_debug2)
-		mx28_reg(hw_apbh_ch5_curcmdar)
-		mx28_reg(hw_apbh_ch5_nxtcmdar)
-		mx28_reg(hw_apbh_ch5_cmd)
-		mx28_reg(hw_apbh_ch5_bar)
-		mx28_reg(hw_apbh_ch5_sema)
-		mx28_reg(hw_apbh_ch5_debug1)
-		mx28_reg(hw_apbh_ch5_debug2)
-		mx28_reg(hw_apbh_ch6_curcmdar)
-		mx28_reg(hw_apbh_ch6_nxtcmdar)
-		mx28_reg(hw_apbh_ch6_cmd)
-		mx28_reg(hw_apbh_ch6_bar)
-		mx28_reg(hw_apbh_ch6_sema)
-		mx28_reg(hw_apbh_ch6_debug1)
-		mx28_reg(hw_apbh_ch6_debug2)
-		mx28_reg(hw_apbh_ch7_curcmdar)
-		mx28_reg(hw_apbh_ch7_nxtcmdar)
-		mx28_reg(hw_apbh_ch7_cmd)
-		mx28_reg(hw_apbh_ch7_bar)
-		mx28_reg(hw_apbh_ch7_sema)
-		mx28_reg(hw_apbh_ch7_debug1)
-		mx28_reg(hw_apbh_ch7_debug2)
-		mx28_reg(hw_apbh_ch8_curcmdar)
-		mx28_reg(hw_apbh_ch8_nxtcmdar)
-		mx28_reg(hw_apbh_ch8_cmd)
-		mx28_reg(hw_apbh_ch8_bar)
-		mx28_reg(hw_apbh_ch8_sema)
-		mx28_reg(hw_apbh_ch8_debug1)
-		mx28_reg(hw_apbh_ch8_debug2)
-		mx28_reg(hw_apbh_ch9_curcmdar)
-		mx28_reg(hw_apbh_ch9_nxtcmdar)
-		mx28_reg(hw_apbh_ch9_cmd)
-		mx28_reg(hw_apbh_ch9_bar)
-		mx28_reg(hw_apbh_ch9_sema)
-		mx28_reg(hw_apbh_ch9_debug1)
-		mx28_reg(hw_apbh_ch9_debug2)
-		mx28_reg(hw_apbh_ch10_curcmdar)
-		mx28_reg(hw_apbh_ch10_nxtcmdar)
-		mx28_reg(hw_apbh_ch10_cmd)
-		mx28_reg(hw_apbh_ch10_bar)
-		mx28_reg(hw_apbh_ch10_sema)
-		mx28_reg(hw_apbh_ch10_debug1)
-		mx28_reg(hw_apbh_ch10_debug2)
-		mx28_reg(hw_apbh_ch11_curcmdar)
-		mx28_reg(hw_apbh_ch11_nxtcmdar)
-		mx28_reg(hw_apbh_ch11_cmd)
-		mx28_reg(hw_apbh_ch11_bar)
-		mx28_reg(hw_apbh_ch11_sema)
-		mx28_reg(hw_apbh_ch11_debug1)
-		mx28_reg(hw_apbh_ch11_debug2)
-		mx28_reg(hw_apbh_ch12_curcmdar)
-		mx28_reg(hw_apbh_ch12_nxtcmdar)
-		mx28_reg(hw_apbh_ch12_cmd)
-		mx28_reg(hw_apbh_ch12_bar)
-		mx28_reg(hw_apbh_ch12_sema)
-		mx28_reg(hw_apbh_ch12_debug1)
-		mx28_reg(hw_apbh_ch12_debug2)
-		mx28_reg(hw_apbh_ch13_curcmdar)
-		mx28_reg(hw_apbh_ch13_nxtcmdar)
-		mx28_reg(hw_apbh_ch13_cmd)
-		mx28_reg(hw_apbh_ch13_bar)
-		mx28_reg(hw_apbh_ch13_sema)
-		mx28_reg(hw_apbh_ch13_debug1)
-		mx28_reg(hw_apbh_ch13_debug2)
-		mx28_reg(hw_apbh_ch14_curcmdar)
-		mx28_reg(hw_apbh_ch14_nxtcmdar)
-		mx28_reg(hw_apbh_ch14_cmd)
-		mx28_reg(hw_apbh_ch14_bar)
-		mx28_reg(hw_apbh_ch14_sema)
-		mx28_reg(hw_apbh_ch14_debug1)
-		mx28_reg(hw_apbh_ch14_debug2)
-		mx28_reg(hw_apbh_ch15_curcmdar)
-		mx28_reg(hw_apbh_ch15_nxtcmdar)
-		mx28_reg(hw_apbh_ch15_cmd)
-		mx28_reg(hw_apbh_ch15_bar)
-		mx28_reg(hw_apbh_ch15_sema)
-		mx28_reg(hw_apbh_ch15_debug1)
-		mx28_reg(hw_apbh_ch15_debug2)
+		mx28_reg_32(hw_apbh_ch0_curcmdar)
+		mx28_reg_32(hw_apbh_ch0_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch0_cmd)
+		mx28_reg_32(hw_apbh_ch0_bar)
+		mx28_reg_32(hw_apbh_ch0_sema)
+		mx28_reg_32(hw_apbh_ch0_debug1)
+		mx28_reg_32(hw_apbh_ch0_debug2)
+		mx28_reg_32(hw_apbh_ch1_curcmdar)
+		mx28_reg_32(hw_apbh_ch1_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch1_cmd)
+		mx28_reg_32(hw_apbh_ch1_bar)
+		mx28_reg_32(hw_apbh_ch1_sema)
+		mx28_reg_32(hw_apbh_ch1_debug1)
+		mx28_reg_32(hw_apbh_ch1_debug2)
+		mx28_reg_32(hw_apbh_ch2_curcmdar)
+		mx28_reg_32(hw_apbh_ch2_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch2_cmd)
+		mx28_reg_32(hw_apbh_ch2_bar)
+		mx28_reg_32(hw_apbh_ch2_sema)
+		mx28_reg_32(hw_apbh_ch2_debug1)
+		mx28_reg_32(hw_apbh_ch2_debug2)
+		mx28_reg_32(hw_apbh_ch3_curcmdar)
+		mx28_reg_32(hw_apbh_ch3_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch3_cmd)
+		mx28_reg_32(hw_apbh_ch3_bar)
+		mx28_reg_32(hw_apbh_ch3_sema)
+		mx28_reg_32(hw_apbh_ch3_debug1)
+		mx28_reg_32(hw_apbh_ch3_debug2)
+		mx28_reg_32(hw_apbh_ch4_curcmdar)
+		mx28_reg_32(hw_apbh_ch4_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch4_cmd)
+		mx28_reg_32(hw_apbh_ch4_bar)
+		mx28_reg_32(hw_apbh_ch4_sema)
+		mx28_reg_32(hw_apbh_ch4_debug1)
+		mx28_reg_32(hw_apbh_ch4_debug2)
+		mx28_reg_32(hw_apbh_ch5_curcmdar)
+		mx28_reg_32(hw_apbh_ch5_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch5_cmd)
+		mx28_reg_32(hw_apbh_ch5_bar)
+		mx28_reg_32(hw_apbh_ch5_sema)
+		mx28_reg_32(hw_apbh_ch5_debug1)
+		mx28_reg_32(hw_apbh_ch5_debug2)
+		mx28_reg_32(hw_apbh_ch6_curcmdar)
+		mx28_reg_32(hw_apbh_ch6_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch6_cmd)
+		mx28_reg_32(hw_apbh_ch6_bar)
+		mx28_reg_32(hw_apbh_ch6_sema)
+		mx28_reg_32(hw_apbh_ch6_debug1)
+		mx28_reg_32(hw_apbh_ch6_debug2)
+		mx28_reg_32(hw_apbh_ch7_curcmdar)
+		mx28_reg_32(hw_apbh_ch7_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch7_cmd)
+		mx28_reg_32(hw_apbh_ch7_bar)
+		mx28_reg_32(hw_apbh_ch7_sema)
+		mx28_reg_32(hw_apbh_ch7_debug1)
+		mx28_reg_32(hw_apbh_ch7_debug2)
+		mx28_reg_32(hw_apbh_ch8_curcmdar)
+		mx28_reg_32(hw_apbh_ch8_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch8_cmd)
+		mx28_reg_32(hw_apbh_ch8_bar)
+		mx28_reg_32(hw_apbh_ch8_sema)
+		mx28_reg_32(hw_apbh_ch8_debug1)
+		mx28_reg_32(hw_apbh_ch8_debug2)
+		mx28_reg_32(hw_apbh_ch9_curcmdar)
+		mx28_reg_32(hw_apbh_ch9_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch9_cmd)
+		mx28_reg_32(hw_apbh_ch9_bar)
+		mx28_reg_32(hw_apbh_ch9_sema)
+		mx28_reg_32(hw_apbh_ch9_debug1)
+		mx28_reg_32(hw_apbh_ch9_debug2)
+		mx28_reg_32(hw_apbh_ch10_curcmdar)
+		mx28_reg_32(hw_apbh_ch10_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch10_cmd)
+		mx28_reg_32(hw_apbh_ch10_bar)
+		mx28_reg_32(hw_apbh_ch10_sema)
+		mx28_reg_32(hw_apbh_ch10_debug1)
+		mx28_reg_32(hw_apbh_ch10_debug2)
+		mx28_reg_32(hw_apbh_ch11_curcmdar)
+		mx28_reg_32(hw_apbh_ch11_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch11_cmd)
+		mx28_reg_32(hw_apbh_ch11_bar)
+		mx28_reg_32(hw_apbh_ch11_sema)
+		mx28_reg_32(hw_apbh_ch11_debug1)
+		mx28_reg_32(hw_apbh_ch11_debug2)
+		mx28_reg_32(hw_apbh_ch12_curcmdar)
+		mx28_reg_32(hw_apbh_ch12_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch12_cmd)
+		mx28_reg_32(hw_apbh_ch12_bar)
+		mx28_reg_32(hw_apbh_ch12_sema)
+		mx28_reg_32(hw_apbh_ch12_debug1)
+		mx28_reg_32(hw_apbh_ch12_debug2)
+		mx28_reg_32(hw_apbh_ch13_curcmdar)
+		mx28_reg_32(hw_apbh_ch13_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch13_cmd)
+		mx28_reg_32(hw_apbh_ch13_bar)
+		mx28_reg_32(hw_apbh_ch13_sema)
+		mx28_reg_32(hw_apbh_ch13_debug1)
+		mx28_reg_32(hw_apbh_ch13_debug2)
+		mx28_reg_32(hw_apbh_ch14_curcmdar)
+		mx28_reg_32(hw_apbh_ch14_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch14_cmd)
+		mx28_reg_32(hw_apbh_ch14_bar)
+		mx28_reg_32(hw_apbh_ch14_sema)
+		mx28_reg_32(hw_apbh_ch14_debug1)
+		mx28_reg_32(hw_apbh_ch14_debug2)
+		mx28_reg_32(hw_apbh_ch15_curcmdar)
+		mx28_reg_32(hw_apbh_ch15_nxtcmdar)
+		mx28_reg_32(hw_apbh_ch15_cmd)
+		mx28_reg_32(hw_apbh_ch15_bar)
+		mx28_reg_32(hw_apbh_ch15_sema)
+		mx28_reg_32(hw_apbh_ch15_debug1)
+		mx28_reg_32(hw_apbh_ch15_debug2)
 	};
 	};
-	mx28_reg(hw_apbh_version)
+	mx28_reg_32(hw_apbh_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h
index cac0470..9243bdd 100644
--- a/arch/arm/include/asm/arch-mx28/regs-bch.h
+++ b/arch/arm/include/asm/arch-mx28/regs-bch.h
@@ -30,30 +30,30 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_bch_regs {
-	mx28_reg(hw_bch_ctrl)
-	mx28_reg(hw_bch_status0)
-	mx28_reg(hw_bch_mode)
-	mx28_reg(hw_bch_encodeptr)
-	mx28_reg(hw_bch_dataptr)
-	mx28_reg(hw_bch_metaptr)
+	mx28_reg_32(hw_bch_ctrl)
+	mx28_reg_32(hw_bch_status0)
+	mx28_reg_32(hw_bch_mode)
+	mx28_reg_32(hw_bch_encodeptr)
+	mx28_reg_32(hw_bch_dataptr)
+	mx28_reg_32(hw_bch_metaptr)
 
 	uint32_t	reserved[4];
 
-	mx28_reg(hw_bch_layoutselect)
-	mx28_reg(hw_bch_flash0layout0)
-	mx28_reg(hw_bch_flash0layout1)
-	mx28_reg(hw_bch_flash1layout0)
-	mx28_reg(hw_bch_flash1layout1)
-	mx28_reg(hw_bch_flash2layout0)
-	mx28_reg(hw_bch_flash2layout1)
-	mx28_reg(hw_bch_flash3layout0)
-	mx28_reg(hw_bch_flash3layout1)
-	mx28_reg(hw_bch_dbgkesread)
-	mx28_reg(hw_bch_dbgcsferead)
-	mx28_reg(hw_bch_dbgsyndegread)
-	mx28_reg(hw_bch_dbgahbmread)
-	mx28_reg(hw_bch_blockname)
-	mx28_reg(hw_bch_version)
+	mx28_reg_32(hw_bch_layoutselect)
+	mx28_reg_32(hw_bch_flash0layout0)
+	mx28_reg_32(hw_bch_flash0layout1)
+	mx28_reg_32(hw_bch_flash1layout0)
+	mx28_reg_32(hw_bch_flash1layout1)
+	mx28_reg_32(hw_bch_flash2layout0)
+	mx28_reg_32(hw_bch_flash2layout1)
+	mx28_reg_32(hw_bch_flash3layout0)
+	mx28_reg_32(hw_bch_flash3layout1)
+	mx28_reg_32(hw_bch_dbgkesread)
+	mx28_reg_32(hw_bch_dbgcsferead)
+	mx28_reg_32(hw_bch_dbgsyndegread)
+	mx28_reg_32(hw_bch_dbgahbmread)
+	mx28_reg_32(hw_bch_blockname)
+	mx28_reg_32(hw_bch_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
index 93d0397..8e666ee 100644
--- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
+++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
@@ -30,38 +30,38 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_clkctrl_regs {
-	mx28_reg(hw_clkctrl_pll0ctrl0)		/* 0x00 */
-	mx28_reg(hw_clkctrl_pll0ctrl1)		/* 0x10 */
-	mx28_reg(hw_clkctrl_pll1ctrl0)		/* 0x20 */
-	mx28_reg(hw_clkctrl_pll1ctrl1)		/* 0x30 */
-	mx28_reg(hw_clkctrl_pll2ctrl0)		/* 0x40 */
-	mx28_reg(hw_clkctrl_cpu)		/* 0x50 */
-	mx28_reg(hw_clkctrl_hbus)		/* 0x60 */
-	mx28_reg(hw_clkctrl_xbus)		/* 0x70 */
-	mx28_reg(hw_clkctrl_xtal)		/* 0x80 */
-	mx28_reg(hw_clkctrl_ssp0)		/* 0x90 */
-	mx28_reg(hw_clkctrl_ssp1)		/* 0xa0 */
-	mx28_reg(hw_clkctrl_ssp2)		/* 0xb0 */
-	mx28_reg(hw_clkctrl_ssp3)		/* 0xc0 */
-	mx28_reg(hw_clkctrl_gpmi)		/* 0xd0 */
-	mx28_reg(hw_clkctrl_spdif)		/* 0xe0 */
-	mx28_reg(hw_clkctrl_emi)		/* 0xf0 */
-	mx28_reg(hw_clkctrl_saif0)		/* 0x100 */
-	mx28_reg(hw_clkctrl_saif1)		/* 0x110 */
-	mx28_reg(hw_clkctrl_lcdif)		/* 0x120 */
-	mx28_reg(hw_clkctrl_etm)		/* 0x130 */
-	mx28_reg(hw_clkctrl_enet)		/* 0x140 */
-	mx28_reg(hw_clkctrl_hsadc)		/* 0x150 */
-	mx28_reg(hw_clkctrl_flexcan)		/* 0x160 */
+	mx28_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	mx28_reg_32(hw_clkctrl_pll0ctrl1)	/* 0x10 */
+	mx28_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
+	mx28_reg_32(hw_clkctrl_pll1ctrl1)	/* 0x30 */
+	mx28_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
+	mx28_reg_32(hw_clkctrl_cpu)		/* 0x50 */
+	mx28_reg_32(hw_clkctrl_hbus)		/* 0x60 */
+	mx28_reg_32(hw_clkctrl_xbus)		/* 0x70 */
+	mx28_reg_32(hw_clkctrl_xtal)		/* 0x80 */
+	mx28_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
+	mx28_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
+	mx28_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
+	mx28_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
+	mx28_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
+	mx28_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
+	mx28_reg_32(hw_clkctrl_emi)		/* 0xf0 */
+	mx28_reg_32(hw_clkctrl_saif0)		/* 0x100 */
+	mx28_reg_32(hw_clkctrl_saif1)		/* 0x110 */
+	mx28_reg_32(hw_clkctrl_lcdif)		/* 0x120 */
+	mx28_reg_32(hw_clkctrl_etm)		/* 0x130 */
+	mx28_reg_32(hw_clkctrl_enet)		/* 0x140 */
+	mx28_reg_32(hw_clkctrl_hsadc)		/* 0x150 */
+	mx28_reg_32(hw_clkctrl_flexcan)		/* 0x160 */
 
 	uint32_t	reserved[16];
 
-	mx28_reg(hw_clkctrl_frac0)		/* 0x1b0 */
-	mx28_reg(hw_clkctrl_frac1)		/* 0x1c0 */
-	mx28_reg(hw_clkctrl_clkseq)		/* 0x1d0 */
-	mx28_reg(hw_clkctrl_reset)		/* 0x1e0 */
-	mx28_reg(hw_clkctrl_status)		/* 0x1f0 */
-	mx28_reg(hw_clkctrl_version)		/* 0x200 */
+	mx28_reg_32(hw_clkctrl_frac0)		/* 0x1b0 */
+	mx28_reg_32(hw_clkctrl_frac1)		/* 0x1c0 */
+	mx28_reg_32(hw_clkctrl_clkseq)		/* 0x1d0 */
+	mx28_reg_32(hw_clkctrl_reset)		/* 0x1e0 */
+	mx28_reg_32(hw_clkctrl_status)		/* 0x1f0 */
+	mx28_reg_32(hw_clkctrl_version)		/* 0x200 */
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h
index efe975b..75cc9a6 100644
--- a/arch/arm/include/asm/arch-mx28/regs-common.h
+++ b/arch/arm/include/asm/arch-mx28/regs-common.h
@@ -47,20 +47,20 @@
  *
  */
 
-#define	__mx28_reg(name)		\
+#define	__mx28_reg_32(name)		\
 	uint32_t name;			\
 	uint32_t name##_set;		\
 	uint32_t name##_clr;		\
 	uint32_t name##_tog;
 
-struct mx28_register {
-	__mx28_reg(reg)
+struct mx28_register_32 {
+	__mx28_reg_32(reg)
 };
 
-#define	mx28_reg(name)					\
+#define	mx28_reg_32(name)				\
 	union {						\
-		struct { __mx28_reg(name) };		\
-		struct mx28_register name##_reg;	\
+		struct { __mx28_reg_32(name) };		\
+		struct mx28_register_32 name##_reg;	\
 	};
 
 #endif	/* __MX28_REGS_COMMON_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
index 0096793..1b487f4 100644
--- a/arch/arm/include/asm/arch-mx28/regs-gpmi.h
+++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
@@ -30,22 +30,22 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_gpmi_regs {
-	mx28_reg(hw_gpmi_ctrl0)
-	mx28_reg(hw_gpmi_compare)
-	mx28_reg(hw_gpmi_eccctrl)
-	mx28_reg(hw_gpmi_ecccount)
-	mx28_reg(hw_gpmi_payload)
-	mx28_reg(hw_gpmi_auxiliary)
-	mx28_reg(hw_gpmi_ctrl1)
-	mx28_reg(hw_gpmi_timing0)
-	mx28_reg(hw_gpmi_timing1)
+	mx28_reg_32(hw_gpmi_ctrl0)
+	mx28_reg_32(hw_gpmi_compare)
+	mx28_reg_32(hw_gpmi_eccctrl)
+	mx28_reg_32(hw_gpmi_ecccount)
+	mx28_reg_32(hw_gpmi_payload)
+	mx28_reg_32(hw_gpmi_auxiliary)
+	mx28_reg_32(hw_gpmi_ctrl1)
+	mx28_reg_32(hw_gpmi_timing0)
+	mx28_reg_32(hw_gpmi_timing1)
 
 	uint32_t	reserved[4];
 
-	mx28_reg(hw_gpmi_data)
-	mx28_reg(hw_gpmi_stat)
-	mx28_reg(hw_gpmi_debug)
-	mx28_reg(hw_gpmi_version)
+	mx28_reg_32(hw_gpmi_data)
+	mx28_reg_32(hw_gpmi_stat)
+	mx28_reg_32(hw_gpmi_debug)
+	mx28_reg_32(hw_gpmi_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h
index 30e0ed7..2e2e814 100644
--- a/arch/arm/include/asm/arch-mx28/regs-i2c.h
+++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_i2c_regs {
-	mx28_reg(hw_i2c_ctrl0)
-	mx28_reg(hw_i2c_timing0)
-	mx28_reg(hw_i2c_timing1)
-	mx28_reg(hw_i2c_timing2)
-	mx28_reg(hw_i2c_ctrl1)
-	mx28_reg(hw_i2c_stat)
-	mx28_reg(hw_i2c_queuectrl)
-	mx28_reg(hw_i2c_queuestat)
-	mx28_reg(hw_i2c_queuecmd)
-	mx28_reg(hw_i2c_queuedata)
-	mx28_reg(hw_i2c_data)
-	mx28_reg(hw_i2c_debug0)
-	mx28_reg(hw_i2c_debug1)
-	mx28_reg(hw_i2c_version)
+	mx28_reg_32(hw_i2c_ctrl0)
+	mx28_reg_32(hw_i2c_timing0)
+	mx28_reg_32(hw_i2c_timing1)
+	mx28_reg_32(hw_i2c_timing2)
+	mx28_reg_32(hw_i2c_ctrl1)
+	mx28_reg_32(hw_i2c_stat)
+	mx28_reg_32(hw_i2c_queuectrl)
+	mx28_reg_32(hw_i2c_queuestat)
+	mx28_reg_32(hw_i2c_queuecmd)
+	mx28_reg_32(hw_i2c_queuedata)
+	mx28_reg_32(hw_i2c_data)
+	mx28_reg_32(hw_i2c_debug0)
+	mx28_reg_32(hw_i2c_debug1)
+	mx28_reg_32(hw_i2c_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
index ea2fd7b..2738035 100644
--- a/arch/arm/include/asm/arch-mx28/regs-ocotp.h
+++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
@@ -30,49 +30,49 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_ocotp_regs {
-	mx28_reg(hw_ocotp_ctrl)		/* 0x0 */
-	mx28_reg(hw_ocotp_data)		/* 0x10 */
-	mx28_reg(hw_ocotp_cust0)	/* 0x20 */
-	mx28_reg(hw_ocotp_cust1)	/* 0x30 */
-	mx28_reg(hw_ocotp_cust2)	/* 0x40 */
-	mx28_reg(hw_ocotp_cust3)	/* 0x50 */
-	mx28_reg(hw_ocotp_crypto0)	/* 0x60 */
-	mx28_reg(hw_ocotp_crypto1)	/* 0x70 */
-	mx28_reg(hw_ocotp_crypto2)	/* 0x80 */
-	mx28_reg(hw_ocotp_crypto3)	/* 0x90 */
-	mx28_reg(hw_ocotp_hwcap0)	/* 0xa0 */
-	mx28_reg(hw_ocotp_hwcap1)	/* 0xb0 */
-	mx28_reg(hw_ocotp_hwcap2)	/* 0xc0 */
-	mx28_reg(hw_ocotp_hwcap3)	/* 0xd0 */
-	mx28_reg(hw_ocotp_hwcap4)	/* 0xe0 */
-	mx28_reg(hw_ocotp_hwcap5)	/* 0xf0 */
-	mx28_reg(hw_ocotp_swcap)	/* 0x100 */
-	mx28_reg(hw_ocotp_custcap)	/* 0x110 */
-	mx28_reg(hw_ocotp_lock)		/* 0x120 */
-	mx28_reg(hw_ocotp_ops0)		/* 0x130 */
-	mx28_reg(hw_ocotp_ops1)		/* 0x140 */
-	mx28_reg(hw_ocotp_ops2)		/* 0x150 */
-	mx28_reg(hw_ocotp_ops3)		/* 0x160 */
-	mx28_reg(hw_ocotp_un0)		/* 0x170 */
-	mx28_reg(hw_ocotp_un1)		/* 0x180 */
-	mx28_reg(hw_ocotp_un2)		/* 0x190 */
-	mx28_reg(hw_ocotp_rom0)		/* 0x1a0 */
-	mx28_reg(hw_ocotp_rom1)		/* 0x1b0 */
-	mx28_reg(hw_ocotp_rom2)		/* 0x1c0 */
-	mx28_reg(hw_ocotp_rom3)		/* 0x1d0 */
-	mx28_reg(hw_ocotp_rom4)		/* 0x1e0 */
-	mx28_reg(hw_ocotp_rom5)		/* 0x1f0 */
-	mx28_reg(hw_ocotp_rom6)		/* 0x200 */
-	mx28_reg(hw_ocotp_rom7)		/* 0x210 */
-	mx28_reg(hw_ocotp_srk0)		/* 0x220 */
-	mx28_reg(hw_ocotp_srk1)		/* 0x230 */
-	mx28_reg(hw_ocotp_srk2)		/* 0x240 */
-	mx28_reg(hw_ocotp_srk3)		/* 0x250 */
-	mx28_reg(hw_ocotp_srk4)		/* 0x260 */
-	mx28_reg(hw_ocotp_srk5)		/* 0x270 */
-	mx28_reg(hw_ocotp_srk6)		/* 0x280 */
-	mx28_reg(hw_ocotp_srk7)		/* 0x290 */
-	mx28_reg(hw_ocotp_version)	/* 0x2a0 */
+	mx28_reg_32(hw_ocotp_ctrl)	/* 0x0 */
+	mx28_reg_32(hw_ocotp_data)	/* 0x10 */
+	mx28_reg_32(hw_ocotp_cust0)	/* 0x20 */
+	mx28_reg_32(hw_ocotp_cust1)	/* 0x30 */
+	mx28_reg_32(hw_ocotp_cust2)	/* 0x40 */
+	mx28_reg_32(hw_ocotp_cust3)	/* 0x50 */
+	mx28_reg_32(hw_ocotp_crypto0)	/* 0x60 */
+	mx28_reg_32(hw_ocotp_crypto1)	/* 0x70 */
+	mx28_reg_32(hw_ocotp_crypto2)	/* 0x80 */
+	mx28_reg_32(hw_ocotp_crypto3)	/* 0x90 */
+	mx28_reg_32(hw_ocotp_hwcap0)	/* 0xa0 */
+	mx28_reg_32(hw_ocotp_hwcap1)	/* 0xb0 */
+	mx28_reg_32(hw_ocotp_hwcap2)	/* 0xc0 */
+	mx28_reg_32(hw_ocotp_hwcap3)	/* 0xd0 */
+	mx28_reg_32(hw_ocotp_hwcap4)	/* 0xe0 */
+	mx28_reg_32(hw_ocotp_hwcap5)	/* 0xf0 */
+	mx28_reg_32(hw_ocotp_swcap)	/* 0x100 */
+	mx28_reg_32(hw_ocotp_custcap)	/* 0x110 */
+	mx28_reg_32(hw_ocotp_lock)	/* 0x120 */
+	mx28_reg_32(hw_ocotp_ops0)	/* 0x130 */
+	mx28_reg_32(hw_ocotp_ops1)	/* 0x140 */
+	mx28_reg_32(hw_ocotp_ops2)	/* 0x150 */
+	mx28_reg_32(hw_ocotp_ops3)	/* 0x160 */
+	mx28_reg_32(hw_ocotp_un0)	/* 0x170 */
+	mx28_reg_32(hw_ocotp_un1)	/* 0x180 */
+	mx28_reg_32(hw_ocotp_un2)	/* 0x190 */
+	mx28_reg_32(hw_ocotp_rom0)	/* 0x1a0 */
+	mx28_reg_32(hw_ocotp_rom1)	/* 0x1b0 */
+	mx28_reg_32(hw_ocotp_rom2)	/* 0x1c0 */
+	mx28_reg_32(hw_ocotp_rom3)	/* 0x1d0 */
+	mx28_reg_32(hw_ocotp_rom4)	/* 0x1e0 */
+	mx28_reg_32(hw_ocotp_rom5)	/* 0x1f0 */
+	mx28_reg_32(hw_ocotp_rom6)	/* 0x200 */
+	mx28_reg_32(hw_ocotp_rom7)	/* 0x210 */
+	mx28_reg_32(hw_ocotp_srk0)	/* 0x220 */
+	mx28_reg_32(hw_ocotp_srk1)	/* 0x230 */
+	mx28_reg_32(hw_ocotp_srk2)	/* 0x240 */
+	mx28_reg_32(hw_ocotp_srk3)	/* 0x250 */
+	mx28_reg_32(hw_ocotp_srk4)	/* 0x260 */
+	mx28_reg_32(hw_ocotp_srk5)	/* 0x270 */
+	mx28_reg_32(hw_ocotp_srk6)	/* 0x280 */
+	mx28_reg_32(hw_ocotp_srk7)	/* 0x290 */
+	mx28_reg_32(hw_ocotp_version)	/* 0x2a0 */
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h
index 73739ca..80dcdf6 100644
--- a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h
+++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h
@@ -30,129 +30,129 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_pinctrl_regs {
-	mx28_reg(hw_pinctrl_ctrl)		/* 0x0 */
+	mx28_reg_32(hw_pinctrl_ctrl)		/* 0x0 */
 
 	uint32_t	reserved1[60];
 
-	mx28_reg(hw_pinctrl_muxsel0)		/* 0x100 */
-	mx28_reg(hw_pinctrl_muxsel1)		/* 0x110 */
-	mx28_reg(hw_pinctrl_muxsel2)		/* 0x120 */
-	mx28_reg(hw_pinctrl_muxsel3)		/* 0x130 */
-	mx28_reg(hw_pinctrl_muxsel4)		/* 0x140 */
-	mx28_reg(hw_pinctrl_muxsel5)		/* 0x150 */
-	mx28_reg(hw_pinctrl_muxsel6)		/* 0x160 */
-	mx28_reg(hw_pinctrl_muxsel7)		/* 0x170 */
-	mx28_reg(hw_pinctrl_muxsel8)		/* 0x180 */
-	mx28_reg(hw_pinctrl_muxsel9)		/* 0x190 */
-	mx28_reg(hw_pinctrl_muxsel10)		/* 0x1a0 */
-	mx28_reg(hw_pinctrl_muxsel11)		/* 0x1b0 */
-	mx28_reg(hw_pinctrl_muxsel12)		/* 0x1c0 */
-	mx28_reg(hw_pinctrl_muxsel13)		/* 0x1d0 */
+	mx28_reg_32(hw_pinctrl_muxsel0)		/* 0x100 */
+	mx28_reg_32(hw_pinctrl_muxsel1)		/* 0x110 */
+	mx28_reg_32(hw_pinctrl_muxsel2)		/* 0x120 */
+	mx28_reg_32(hw_pinctrl_muxsel3)		/* 0x130 */
+	mx28_reg_32(hw_pinctrl_muxsel4)		/* 0x140 */
+	mx28_reg_32(hw_pinctrl_muxsel5)		/* 0x150 */
+	mx28_reg_32(hw_pinctrl_muxsel6)		/* 0x160 */
+	mx28_reg_32(hw_pinctrl_muxsel7)		/* 0x170 */
+	mx28_reg_32(hw_pinctrl_muxsel8)		/* 0x180 */
+	mx28_reg_32(hw_pinctrl_muxsel9)		/* 0x190 */
+	mx28_reg_32(hw_pinctrl_muxsel10)	/* 0x1a0 */
+	mx28_reg_32(hw_pinctrl_muxsel11)	/* 0x1b0 */
+	mx28_reg_32(hw_pinctrl_muxsel12)	/* 0x1c0 */
+	mx28_reg_32(hw_pinctrl_muxsel13)	/* 0x1d0 */
 
 	uint32_t	reserved2[72];
 
-	mx28_reg(hw_pinctrl_drive0)		/* 0x300 */
-	mx28_reg(hw_pinctrl_drive1)		/* 0x310 */
-	mx28_reg(hw_pinctrl_drive2)		/* 0x320 */
-	mx28_reg(hw_pinctrl_drive3)		/* 0x330 */
-	mx28_reg(hw_pinctrl_drive4)		/* 0x340 */
-	mx28_reg(hw_pinctrl_drive5)		/* 0x350 */
-	mx28_reg(hw_pinctrl_drive6)		/* 0x360 */
-	mx28_reg(hw_pinctrl_drive7)		/* 0x370 */
-	mx28_reg(hw_pinctrl_drive8)		/* 0x380 */
-	mx28_reg(hw_pinctrl_drive9)		/* 0x390 */
-	mx28_reg(hw_pinctrl_drive10)		/* 0x3a0 */
-	mx28_reg(hw_pinctrl_drive11)		/* 0x3b0 */
-	mx28_reg(hw_pinctrl_drive12)		/* 0x3c0 */
-	mx28_reg(hw_pinctrl_drive13)		/* 0x3d0 */
-	mx28_reg(hw_pinctrl_drive14)		/* 0x3e0 */
-	mx28_reg(hw_pinctrl_drive15)		/* 0x3f0 */
-	mx28_reg(hw_pinctrl_drive16)		/* 0x400 */
-	mx28_reg(hw_pinctrl_drive17)		/* 0x410 */
-	mx28_reg(hw_pinctrl_drive18)		/* 0x420 */
-	mx28_reg(hw_pinctrl_drive19)		/* 0x430 */
+	mx28_reg_32(hw_pinctrl_drive0)		/* 0x300 */
+	mx28_reg_32(hw_pinctrl_drive1)		/* 0x310 */
+	mx28_reg_32(hw_pinctrl_drive2)		/* 0x320 */
+	mx28_reg_32(hw_pinctrl_drive3)		/* 0x330 */
+	mx28_reg_32(hw_pinctrl_drive4)		/* 0x340 */
+	mx28_reg_32(hw_pinctrl_drive5)		/* 0x350 */
+	mx28_reg_32(hw_pinctrl_drive6)		/* 0x360 */
+	mx28_reg_32(hw_pinctrl_drive7)		/* 0x370 */
+	mx28_reg_32(hw_pinctrl_drive8)		/* 0x380 */
+	mx28_reg_32(hw_pinctrl_drive9)		/* 0x390 */
+	mx28_reg_32(hw_pinctrl_drive10)		/* 0x3a0 */
+	mx28_reg_32(hw_pinctrl_drive11)		/* 0x3b0 */
+	mx28_reg_32(hw_pinctrl_drive12)		/* 0x3c0 */
+	mx28_reg_32(hw_pinctrl_drive13)		/* 0x3d0 */
+	mx28_reg_32(hw_pinctrl_drive14)		/* 0x3e0 */
+	mx28_reg_32(hw_pinctrl_drive15)		/* 0x3f0 */
+	mx28_reg_32(hw_pinctrl_drive16)		/* 0x400 */
+	mx28_reg_32(hw_pinctrl_drive17)		/* 0x410 */
+	mx28_reg_32(hw_pinctrl_drive18)		/* 0x420 */
+	mx28_reg_32(hw_pinctrl_drive19)		/* 0x430 */
 
 	uint32_t	reserved3[112];
 
-	mx28_reg(hw_pinctrl_pull0)		/* 0x600 */
-	mx28_reg(hw_pinctrl_pull1)		/* 0x610 */
-	mx28_reg(hw_pinctrl_pull2)		/* 0x620 */
-	mx28_reg(hw_pinctrl_pull3)		/* 0x630 */
-	mx28_reg(hw_pinctrl_pull4)		/* 0x640 */
-	mx28_reg(hw_pinctrl_pull5)		/* 0x650 */
-	mx28_reg(hw_pinctrl_pull6)		/* 0x660 */
+	mx28_reg_32(hw_pinctrl_pull0)		/* 0x600 */
+	mx28_reg_32(hw_pinctrl_pull1)		/* 0x610 */
+	mx28_reg_32(hw_pinctrl_pull2)		/* 0x620 */
+	mx28_reg_32(hw_pinctrl_pull3)		/* 0x630 */
+	mx28_reg_32(hw_pinctrl_pull4)		/* 0x640 */
+	mx28_reg_32(hw_pinctrl_pull5)		/* 0x650 */
+	mx28_reg_32(hw_pinctrl_pull6)		/* 0x660 */
 
 	uint32_t	reserved4[36];
 
-	mx28_reg(hw_pinctrl_dout0)		/* 0x700 */
-	mx28_reg(hw_pinctrl_dout1)		/* 0x710 */
-	mx28_reg(hw_pinctrl_dout2)		/* 0x720 */
-	mx28_reg(hw_pinctrl_dout3)		/* 0x730 */
-	mx28_reg(hw_pinctrl_dout4)		/* 0x740 */
+	mx28_reg_32(hw_pinctrl_dout0)		/* 0x700 */
+	mx28_reg_32(hw_pinctrl_dout1)		/* 0x710 */
+	mx28_reg_32(hw_pinctrl_dout2)		/* 0x720 */
+	mx28_reg_32(hw_pinctrl_dout3)		/* 0x730 */
+	mx28_reg_32(hw_pinctrl_dout4)		/* 0x740 */
 
 	uint32_t	reserved5[108];
 
-	mx28_reg(hw_pinctrl_din0)		/* 0x900 */
-	mx28_reg(hw_pinctrl_din1)		/* 0x910 */
-	mx28_reg(hw_pinctrl_din2)		/* 0x920 */
-	mx28_reg(hw_pinctrl_din3)		/* 0x930 */
-	mx28_reg(hw_pinctrl_din4)		/* 0x940 */
+	mx28_reg_32(hw_pinctrl_din0)		/* 0x900 */
+	mx28_reg_32(hw_pinctrl_din1)		/* 0x910 */
+	mx28_reg_32(hw_pinctrl_din2)		/* 0x920 */
+	mx28_reg_32(hw_pinctrl_din3)		/* 0x930 */
+	mx28_reg_32(hw_pinctrl_din4)		/* 0x940 */
 
 	uint32_t	reserved6[108];
 
-	mx28_reg(hw_pinctrl_doe0)		/* 0xb00 */
-	mx28_reg(hw_pinctrl_doe1)		/* 0xb10 */
-	mx28_reg(hw_pinctrl_doe2)		/* 0xb20 */
-	mx28_reg(hw_pinctrl_doe3)		/* 0xb30 */
-	mx28_reg(hw_pinctrl_doe4)		/* 0xb40 */
+	mx28_reg_32(hw_pinctrl_doe0)		/* 0xb00 */
+	mx28_reg_32(hw_pinctrl_doe1)		/* 0xb10 */
+	mx28_reg_32(hw_pinctrl_doe2)		/* 0xb20 */
+	mx28_reg_32(hw_pinctrl_doe3)		/* 0xb30 */
+	mx28_reg_32(hw_pinctrl_doe4)		/* 0xb40 */
 
 	uint32_t	reserved7[300];
 
-	mx28_reg(hw_pinctrl_pin2irq0)		/* 0x1000 */
-	mx28_reg(hw_pinctrl_pin2irq1)		/* 0x1010 */
-	mx28_reg(hw_pinctrl_pin2irq2)		/* 0x1020 */
-	mx28_reg(hw_pinctrl_pin2irq3)		/* 0x1030 */
-	mx28_reg(hw_pinctrl_pin2irq4)		/* 0x1040 */
+	mx28_reg_32(hw_pinctrl_pin2irq0)	/* 0x1000 */
+	mx28_reg_32(hw_pinctrl_pin2irq1)	/* 0x1010 */
+	mx28_reg_32(hw_pinctrl_pin2irq2)	/* 0x1020 */
+	mx28_reg_32(hw_pinctrl_pin2irq3)	/* 0x1030 */
+	mx28_reg_32(hw_pinctrl_pin2irq4)	/* 0x1040 */
 
 	uint32_t	reserved8[44];
 
-	mx28_reg(hw_pinctrl_irqen0)		/* 0x1100 */
-	mx28_reg(hw_pinctrl_irqen1)		/* 0x1110 */
-	mx28_reg(hw_pinctrl_irqen2)		/* 0x1120 */
-	mx28_reg(hw_pinctrl_irqen3)		/* 0x1130 */
-	mx28_reg(hw_pinctrl_irqen4)		/* 0x1140 */
+	mx28_reg_32(hw_pinctrl_irqen0)		/* 0x1100 */
+	mx28_reg_32(hw_pinctrl_irqen1)		/* 0x1110 */
+	mx28_reg_32(hw_pinctrl_irqen2)		/* 0x1120 */
+	mx28_reg_32(hw_pinctrl_irqen3)		/* 0x1130 */
+	mx28_reg_32(hw_pinctrl_irqen4)		/* 0x1140 */
 
 	uint32_t	reserved9[44];
 
-	mx28_reg(hw_pinctrl_irqlevel0)		/* 0x1200 */
-	mx28_reg(hw_pinctrl_irqlevel1)		/* 0x1210 */
-	mx28_reg(hw_pinctrl_irqlevel2)		/* 0x1220 */
-	mx28_reg(hw_pinctrl_irqlevel3)		/* 0x1230 */
-	mx28_reg(hw_pinctrl_irqlevel4)		/* 0x1240 */
+	mx28_reg_32(hw_pinctrl_irqlevel0)	/* 0x1200 */
+	mx28_reg_32(hw_pinctrl_irqlevel1)	/* 0x1210 */
+	mx28_reg_32(hw_pinctrl_irqlevel2)	/* 0x1220 */
+	mx28_reg_32(hw_pinctrl_irqlevel3)	/* 0x1230 */
+	mx28_reg_32(hw_pinctrl_irqlevel4)	/* 0x1240 */
 
 	uint32_t	reserved10[44];
 
-	mx28_reg(hw_pinctrl_irqpol0)		/* 0x1300 */
-	mx28_reg(hw_pinctrl_irqpol1)		/* 0x1310 */
-	mx28_reg(hw_pinctrl_irqpol2)		/* 0x1320 */
-	mx28_reg(hw_pinctrl_irqpol3)		/* 0x1330 */
-	mx28_reg(hw_pinctrl_irqpol4)		/* 0x1340 */
+	mx28_reg_32(hw_pinctrl_irqpol0)		/* 0x1300 */
+	mx28_reg_32(hw_pinctrl_irqpol1)		/* 0x1310 */
+	mx28_reg_32(hw_pinctrl_irqpol2)		/* 0x1320 */
+	mx28_reg_32(hw_pinctrl_irqpol3)		/* 0x1330 */
+	mx28_reg_32(hw_pinctrl_irqpol4)		/* 0x1340 */
 
 	uint32_t	reserved11[44];
 
-	mx28_reg(hw_pinctrl_irqstat0)		/* 0x1400 */
-	mx28_reg(hw_pinctrl_irqstat1)		/* 0x1410 */
-	mx28_reg(hw_pinctrl_irqstat2)		/* 0x1420 */
-	mx28_reg(hw_pinctrl_irqstat3)		/* 0x1430 */
-	mx28_reg(hw_pinctrl_irqstat4)		/* 0x1440 */
+	mx28_reg_32(hw_pinctrl_irqstat0)	/* 0x1400 */
+	mx28_reg_32(hw_pinctrl_irqstat1)	/* 0x1410 */
+	mx28_reg_32(hw_pinctrl_irqstat2)	/* 0x1420 */
+	mx28_reg_32(hw_pinctrl_irqstat3)	/* 0x1430 */
+	mx28_reg_32(hw_pinctrl_irqstat4)	/* 0x1440 */
 
 	uint32_t	reserved12[380];
 
-	mx28_reg(hw_pinctrl_emi_odt_ctrl)	/* 0x1a40 */
+	mx28_reg_32(hw_pinctrl_emi_odt_ctrl)	/* 0x1a40 */
 
 	uint32_t	reserved13[76];
 
-	mx28_reg(hw_pinctrl_emi_ds_ctrl)	/* 0x1b80 */
+	mx28_reg_32(hw_pinctrl_emi_ds_ctrl)	/* 0x1b80 */
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h
index 9da63ad..8eadc6d 100644
--- a/arch/arm/include/asm/arch-mx28/regs-power.h
+++ b/arch/arm/include/asm/arch-mx28/regs-power.h
@@ -26,10 +26,10 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_power_regs {
-	mx28_reg(hw_power_ctrl)
-	mx28_reg(hw_power_5vctrl)
-	mx28_reg(hw_power_minpwr)
-	mx28_reg(hw_power_charge)
+	mx28_reg_32(hw_power_ctrl)
+	mx28_reg_32(hw_power_5vctrl)
+	mx28_reg_32(hw_power_minpwr)
+	mx28_reg_32(hw_power_charge)
 	uint32_t	hw_power_vdddctrl;
 	uint32_t	reserved_vddd[3];
 	uint32_t	hw_power_vddactrl;
@@ -44,23 +44,23 @@ struct mx28_power_regs {
 	uint32_t	reserved_misc[3];
 	uint32_t	hw_power_dclimits;
 	uint32_t	reserved_dclimits[3];
-	mx28_reg(hw_power_loopctrl)
+	mx28_reg_32(hw_power_loopctrl)
 	uint32_t	hw_power_sts;
 	uint32_t	reserved_sts[3];
-	mx28_reg(hw_power_speed)
+	mx28_reg_32(hw_power_speed)
 	uint32_t	hw_power_battmonitor;
 	uint32_t	reserved_battmonitor[3];
 
 	uint32_t	reserved[4];
 
-	mx28_reg(hw_power_reset)
-	mx28_reg(hw_power_debug)
-	mx28_reg(hw_power_thermal)
-	mx28_reg(hw_power_usb1ctrl)
-	mx28_reg(hw_power_special)
-	mx28_reg(hw_power_version)
-	mx28_reg(hw_power_anaclkctrl)
-	mx28_reg(hw_power_refctrl)
+	mx28_reg_32(hw_power_reset)
+	mx28_reg_32(hw_power_debug)
+	mx28_reg_32(hw_power_thermal)
+	mx28_reg_32(hw_power_usb1ctrl)
+	mx28_reg_32(hw_power_special)
+	mx28_reg_32(hw_power_version)
+	mx28_reg_32(hw_power_anaclkctrl)
+	mx28_reg_32(hw_power_refctrl)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h
index fe2fda9..e605a03 100644
--- a/arch/arm/include/asm/arch-mx28/regs-rtc.h
+++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_rtc_regs {
-	mx28_reg(hw_rtc_ctrl)
-	mx28_reg(hw_rtc_stat)
-	mx28_reg(hw_rtc_milliseconds)
-	mx28_reg(hw_rtc_seconds)
-	mx28_reg(hw_rtc_rtc_alarm)
-	mx28_reg(hw_rtc_watchdog)
-	mx28_reg(hw_rtc_persistent0)
-	mx28_reg(hw_rtc_persistent1)
-	mx28_reg(hw_rtc_persistent2)
-	mx28_reg(hw_rtc_persistent3)
-	mx28_reg(hw_rtc_persistent4)
-	mx28_reg(hw_rtc_persistent5)
-	mx28_reg(hw_rtc_debug)
-	mx28_reg(hw_rtc_version)
+	mx28_reg_32(hw_rtc_ctrl)
+	mx28_reg_32(hw_rtc_stat)
+	mx28_reg_32(hw_rtc_milliseconds)
+	mx28_reg_32(hw_rtc_seconds)
+	mx28_reg_32(hw_rtc_rtc_alarm)
+	mx28_reg_32(hw_rtc_watchdog)
+	mx28_reg_32(hw_rtc_persistent0)
+	mx28_reg_32(hw_rtc_persistent1)
+	mx28_reg_32(hw_rtc_persistent2)
+	mx28_reg_32(hw_rtc_persistent3)
+	mx28_reg_32(hw_rtc_persistent4)
+	mx28_reg_32(hw_rtc_persistent5)
+	mx28_reg_32(hw_rtc_debug)
+	mx28_reg_32(hw_rtc_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h
index ab3870c..be71d48 100644
--- a/arch/arm/include/asm/arch-mx28/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h
@@ -29,26 +29,26 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_ssp_regs {
-	mx28_reg(hw_ssp_ctrl0)
-	mx28_reg(hw_ssp_cmd0)
-	mx28_reg(hw_ssp_cmd1)
-	mx28_reg(hw_ssp_xfer_size)
-	mx28_reg(hw_ssp_block_size)
-	mx28_reg(hw_ssp_compref)
-	mx28_reg(hw_ssp_compmask)
-	mx28_reg(hw_ssp_timing)
-	mx28_reg(hw_ssp_ctrl1)
-	mx28_reg(hw_ssp_data)
-	mx28_reg(hw_ssp_sdresp0)
-	mx28_reg(hw_ssp_sdresp1)
-	mx28_reg(hw_ssp_sdresp2)
-	mx28_reg(hw_ssp_sdresp3)
-	mx28_reg(hw_ssp_ddr_ctrl)
-	mx28_reg(hw_ssp_dll_ctrl)
-	mx28_reg(hw_ssp_status)
-	mx28_reg(hw_ssp_dll_sts)
-	mx28_reg(hw_ssp_debug)
-	mx28_reg(hw_ssp_version)
+	mx28_reg_32(hw_ssp_ctrl0)
+	mx28_reg_32(hw_ssp_cmd0)
+	mx28_reg_32(hw_ssp_cmd1)
+	mx28_reg_32(hw_ssp_xfer_size)
+	mx28_reg_32(hw_ssp_block_size)
+	mx28_reg_32(hw_ssp_compref)
+	mx28_reg_32(hw_ssp_compmask)
+	mx28_reg_32(hw_ssp_timing)
+	mx28_reg_32(hw_ssp_ctrl1)
+	mx28_reg_32(hw_ssp_data)
+	mx28_reg_32(hw_ssp_sdresp0)
+	mx28_reg_32(hw_ssp_sdresp1)
+	mx28_reg_32(hw_ssp_sdresp2)
+	mx28_reg_32(hw_ssp_sdresp3)
+	mx28_reg_32(hw_ssp_ddr_ctrl)
+	mx28_reg_32(hw_ssp_dll_ctrl)
+	mx28_reg_32(hw_ssp_status)
+	mx28_reg_32(hw_ssp_dll_sts)
+	mx28_reg_32(hw_ssp_debug)
+	mx28_reg_32(hw_ssp_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h
index 1b941cf..3e8dfe7 100644
--- a/arch/arm/include/asm/arch-mx28/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h
@@ -29,25 +29,25 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_timrot_regs {
-	mx28_reg(hw_timrot_rotctrl)
-	mx28_reg(hw_timrot_rotcount)
-	mx28_reg(hw_timrot_timctrl0)
-	mx28_reg(hw_timrot_running_count0)
-	mx28_reg(hw_timrot_fixed_count0)
-	mx28_reg(hw_timrot_match_count0)
-	mx28_reg(hw_timrot_timctrl1)
-	mx28_reg(hw_timrot_running_count1)
-	mx28_reg(hw_timrot_fixed_count1)
-	mx28_reg(hw_timrot_match_count1)
-	mx28_reg(hw_timrot_timctrl2)
-	mx28_reg(hw_timrot_running_count2)
-	mx28_reg(hw_timrot_fixed_count2)
-	mx28_reg(hw_timrot_match_count2)
-	mx28_reg(hw_timrot_timctrl3)
-	mx28_reg(hw_timrot_running_count3)
-	mx28_reg(hw_timrot_fixed_count3)
-	mx28_reg(hw_timrot_match_count3)
-	mx28_reg(hw_timrot_version)
+	mx28_reg_32(hw_timrot_rotctrl)
+	mx28_reg_32(hw_timrot_rotcount)
+	mx28_reg_32(hw_timrot_timctrl0)
+	mx28_reg_32(hw_timrot_running_count0)
+	mx28_reg_32(hw_timrot_fixed_count0)
+	mx28_reg_32(hw_timrot_match_count0)
+	mx28_reg_32(hw_timrot_timctrl1)
+	mx28_reg_32(hw_timrot_running_count1)
+	mx28_reg_32(hw_timrot_fixed_count1)
+	mx28_reg_32(hw_timrot_match_count1)
+	mx28_reg_32(hw_timrot_timctrl2)
+	mx28_reg_32(hw_timrot_running_count2)
+	mx28_reg_32(hw_timrot_fixed_count2)
+	mx28_reg_32(hw_timrot_match_count2)
+	mx28_reg_32(hw_timrot_timctrl3)
+	mx28_reg_32(hw_timrot_running_count3)
+	mx28_reg_32(hw_timrot_fixed_count3)
+	mx28_reg_32(hw_timrot_match_count3)
+	mx28_reg_32(hw_timrot_version)
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h
index e823e19..0291d81 100644
--- a/arch/arm/include/asm/arch-mx28/regs-usbphy.h
+++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h
@@ -24,16 +24,16 @@
 #define __REGS_USBPHY_H__
 
 struct mx28_usbphy_regs {
-	mx28_reg(hw_usbphy_pwd)
-	mx28_reg(hw_usbphy_tx)
-	mx28_reg(hw_usbphy_rx)
-	mx28_reg(hw_usbphy_ctrl)
-	mx28_reg(hw_usbphy_status)
-	mx28_reg(hw_usbphy_debug)
-	mx28_reg(hw_usbphy_debug0_status)
-	mx28_reg(hw_usbphy_debug1)
-	mx28_reg(hw_usbphy_version)
-	mx28_reg(hw_usbphy_ip)
+	mx28_reg_32(hw_usbphy_pwd)
+	mx28_reg_32(hw_usbphy_tx)
+	mx28_reg_32(hw_usbphy_rx)
+	mx28_reg_32(hw_usbphy_ctrl)
+	mx28_reg_32(hw_usbphy_status)
+	mx28_reg_32(hw_usbphy_debug)
+	mx28_reg_32(hw_usbphy_debug0_status)
+	mx28_reg_32(hw_usbphy_debug1)
+	mx28_reg_32(hw_usbphy_version)
+	mx28_reg_32(hw_usbphy_ip)
 };
 
 #define	USBPHY_PWD_RXPWDRX				(1 << 20)
diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h
index f101494..15d8de3 100644
--- a/arch/arm/include/asm/arch-mx28/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx28/sys_proto.h
@@ -23,9 +23,13 @@
 #ifndef __MX28_H__
 #define __MX28_H__
 
-int mx28_reset_block(struct mx28_register *reg);
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout);
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
+int mx28_reset_block(struct mx28_register_32 *reg);
+int mx28_wait_mask_set(struct mx28_register_32 *reg,
+		       uint32_t mask,
+		       int timeout);
+int mx28_wait_mask_clr(struct mx28_register_32 *reg,
+		       uint32_t mask,
+		       int timeout);
 
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
 
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index 0365812..38dbc81 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DIN(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
 }
@@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOUT(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	if (value)
 		writel(1 << PAD_PIN(gpio), &reg->reg_set);
@@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_clr);
 
@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_set);
 
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
index c795f23..e1bd37e 100644
--- a/drivers/usb/host/ehci-mxs.c
+++ b/drivers/usb/host/ehci-mxs.c
@@ -75,8 +75,8 @@ int ehci_hcd_init(void)
 
 	int ret;
 	uint32_t usb_base, cap_base;
-	struct mx28_register *digctl_ctrl =
-		(struct mx28_register *)HW_DIGCTL_CTRL;
+	struct mx28_register_32 *digctl_ctrl =
+		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
@@ -119,8 +119,8 @@ int ehci_hcd_stop(void)
 {
 	int ret;
 	uint32_t tmp;
-	struct mx28_register *digctl_ctrl =
-		(struct mx28_register *)HW_DIGCTL_CTRL;
+	struct mx28_register_32 *digctl_ctrl =
+		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-- 
1.7.0.4

[U-Boot] [PATCH 2/4 v4] Introducing 8-bit wide register, mx28_register_8

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This patch introduces an 8-bit register, mx28_register_8, in order to
prepare for fixing erroneous 32-bit wide access of registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by: Robert Delien <robert@delien.nl>
---
 arch/arm/include/asm/arch-mx28/regs-common.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h
index 75cc9a6..94b512d 100644
--- a/arch/arm/include/asm/arch-mx28/regs-common.h
+++ b/arch/arm/include/asm/arch-mx28/regs-common.h
@@ -47,16 +47,32 @@
  *
  */
 
+#define	__mx28_reg_8(name)		\
+	uint8_t	name[4];		\
+	uint8_t	name##_set[4];		\
+	uint8_t	name##_clr[4];		\
+	uint8_t	name##_tog[4];		\
+
 #define	__mx28_reg_32(name)		\
 	uint32_t name;			\
 	uint32_t name##_set;		\
 	uint32_t name##_clr;		\
 	uint32_t name##_tog;
 
+struct mx28_register_8 {
+	__mx28_reg_8(reg)
+};
+
 struct mx28_register_32 {
 	__mx28_reg_32(reg)
 };
 
+#define	mx28_reg_8(name)				\
+	union {						\
+		struct { __mx28_reg_8(name) };		\
+		struct mx28_register_32 name##_reg;	\
+	};
+
 #define	mx28_reg_32(name)				\
 	union {						\
 		struct { __mx28_reg_32(name) };		\
-- 
1.7.0.4

[U-Boot] [PATCH 3/4 v4] Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by: Robert Delien <robert@delien.nl>
---
 arch/arm/cpu/arm926ejs/mx28/clock.c           |   70 ++++++++++---------------
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c    |   26 ++++-----
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   44 +++++-----------
 3 files changed, 52 insertions(+), 88 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c
index 9d3a018..5bc7825 100644
--- a/arch/arm/cpu/arm926ejs/mx28/clock.c
+++ b/arch/arm/cpu/arm926ejs/mx28/clock.c
@@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t clkctrl, clkseq, clkfrac;
-	uint32_t frac, div;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
 
@@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void)
 	}
 
 	/* REF Path */
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-	frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
@@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
-		CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
@@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
-		CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t div;
+	int io_reg;
 
 	if (freq == 0)
 		return;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return;
 
 	div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
@@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	if (div > 35)
 		div = 35;
 
-	if (io == MXC_IOCLK0) {
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO0FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	} else {
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO1FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	}
+	io_reg = MXC_IOCLK1 - io;	/* Register order is reversed */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
 }
 
 /*
@@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	uint32_t tmp, ret;
+	uint8_t ret;
+	int io_reg;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return 0;
 
-	tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+	io_reg = MXC_IOCLK1 - io;	/* Register order is reversed */
 
-	if (io == MXC_IOCLK0)
-		ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO0FRAC_OFFSET;
-	else
-		ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+	ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
+		CLKCTRL_FRAC_FRAC_MASK;
 
 	return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
 }
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 00493b8..f2fab7c 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -86,22 +86,20 @@ void mx28_mem_init_clock(void)
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Gate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-	/* EMI = 205MHz */
-	writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
-	writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
-		CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
 	/* Ungate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
 
 	early_delay(11000);
 
+	/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
 	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
 		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
 		&clkctrl_regs->hw_clkctrl_emi);
@@ -118,10 +116,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	/* CPU = 454MHz and ungate CPU clock */
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-		CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
-		19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+	 * and ungate CPU clock */
+	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
 	/* Set CPU bypass */
 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
index 8e666ee..3c4947d 100644
--- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
+++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
@@ -56,8 +56,8 @@ struct mx28_clkctrl_regs {
 
 	uint32_t	reserved[16];
 
-	mx28_reg_32(hw_clkctrl_frac0)		/* 0x1b0 */
-	mx28_reg_32(hw_clkctrl_frac1)		/* 0x1c0 */
+	mx28_reg_8(hw_clkctrl_frac0)		/* 0x1b0 */
+	mx28_reg_8(hw_clkctrl_frac1)		/* 0x1c0 */
 	mx28_reg_32(hw_clkctrl_clkseq)		/* 0x1d0 */
 	mx28_reg_32(hw_clkctrl_reset)		/* 0x1e0 */
 	mx28_reg_32(hw_clkctrl_status)		/* 0x1f0 */
@@ -248,35 +248,17 @@ struct mx28_clkctrl_regs {
 #define	CLKCTRL_FLEXCAN_STOP_CAN1		(1 << 28)
 #define	CLKCTRL_FLEXCAN_CAN1_STATUS		(1 << 27)
 
-#define	CLKCTRL_FRAC0_CLKGATEIO0		(1 << 31)
-#define	CLKCTRL_FRAC0_IO0_STABLE		(1 << 30)
-#define	CLKCTRL_FRAC0_IO0FRAC_MASK		(0x3f << 24)
-#define	CLKCTRL_FRAC0_IO0FRAC_OFFSET		24
-#define	CLKCTRL_FRAC0_CLKGATEIO1		(1 << 23)
-#define	CLKCTRL_FRAC0_IO1_STABLE		(1 << 22)
-#define	CLKCTRL_FRAC0_IO1FRAC_MASK		(0x3f << 16)
-#define	CLKCTRL_FRAC0_IO1FRAC_OFFSET		16
-#define	CLKCTRL_FRAC0_CLKGATEEMI		(1 << 15)
-#define	CLKCTRL_FRAC0_EMI_STABLE		(1 << 14)
-#define	CLKCTRL_FRAC0_EMIFRAC_MASK		(0x3f << 8)
-#define	CLKCTRL_FRAC0_EMIFRAC_OFFSET		8
-#define	CLKCTRL_FRAC0_CLKGATECPU		(1 << 7)
-#define	CLKCTRL_FRAC0_CPU_STABLE		(1 << 6)
-#define	CLKCTRL_FRAC0_CPUFRAC_MASK		0x3f
-#define	CLKCTRL_FRAC0_CPUFRAC_OFFSET		0
-
-#define	CLKCTRL_FRAC1_CLKGATEGPMI		(1 << 23)
-#define	CLKCTRL_FRAC1_GPMI_STABLE		(1 << 22)
-#define	CLKCTRL_FRAC1_GPMIFRAC_MASK		(0x3f << 16)
-#define	CLKCTRL_FRAC1_GPMIFRAC_OFFSET		16
-#define	CLKCTRL_FRAC1_CLKGATEHSADC		(1 << 15)
-#define	CLKCTRL_FRAC1_HSADC_STABLE		(1 << 14)
-#define	CLKCTRL_FRAC1_HSADCFRAC_MASK		(0x3f << 8)
-#define	CLKCTRL_FRAC1_HSADCFRAC_OFFSET		8
-#define	CLKCTRL_FRAC1_CLKGATEPIX		(1 << 7)
-#define	CLKCTRL_FRAC1_PIX_STABLE		(1 << 6)
-#define	CLKCTRL_FRAC1_PIXFRAC_MASK		0x3f
-#define	CLKCTRL_FRAC1_PIXFRAC_OFFSET		0
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_IO1			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_PIX			0
+#define	CLKCTRL_FRAC1_HSADC			1
+#define	CLKCTRL_FRAC1_GPMI			2
 
 #define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 18)
 #define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF		(1 << 14)
-- 
1.7.0.4

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[robert at delien.nl]

From: Robert Delien <robert@delien.nl>

This patch prevents the needless switching on and off of PLL bypass
mode. With this patch in place, single-stepping through the SPL is
now possible.

Signed-off-by: Robert Delien <robert@delien.nl>
---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c   |    4 ----
 arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |   24 ------------------------
 2 files changed, 0 insertions(+), 28 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index f2fab7c..cf4361c 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
 		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
-	/* Set CPU bypass */
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_set);
-
 	/* HBUS = 151MHz */
 	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
 	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 380b120..5e21a1e 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -30,28 +30,6 @@
 
 #include "mx28_init.h"
 
-void mx28_power_clock2xtal(void)
-{
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
-	/* Set XTAL as CPU reference clock */
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_set);
-}
-
-void mx28_power_clock2pll(void)
-{
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
-	writel(CLKCTRL_PLL0CTRL0_POWER,
-		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
-	early_delay(100);
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_clr);
-}
-
 void mx28_power_clear_auto_restart(void)
 {
 	struct mx28_rtc_regs *rtc_regs =
@@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)
 	mx28_src_power_init();
 
 	mx28_5v_boot();
-	mx28_power_clock2pll();
 
 	mx28_init_batt_bo();
 	mx28_switch_vddd_to_dcdc_source();
@@ -880,7 +857,6 @@ void mx28_power_init(void)
 	struct mx28_power_regs *power_regs =
 		(struct mx28_power_regs *)MXS_POWER_BASE;
 
-	mx28_power_clock2xtal();
 	mx28_power_clear_auto_restart();
 	mx28_power_set_linreg();
 	mx28_power_setup_5v_detect();
-- 
1.7.0.4

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Marek Vasut]

> From: Robert Delien <robert@delien.nl>
> 
> This patch prevents the needless switching on and off of PLL bypass
> mode. With this patch in place, single-stepping through the SPL is
> now possible.

Why did FSL have it in the bootlets though? Fabio, can you explain?

M

> 
> Signed-off-by: Robert Delien <robert@delien.nl>
> ---
>  arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c   |    4 ----
>  arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |   24
> ------------------------ 2 files changed, 0 insertions(+), 28 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index f2fab7c..cf4361c 100644
> --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> @@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)
>  	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
>  		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
> 
> -	/* Set CPU bypass */
> -	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
> -		&clkctrl_regs->hw_clkctrl_clkseq_set);
> -
>  	/* HBUS = 151MHz */
>  	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
>  	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
> diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 380b120..5e21a1e
> 100644
> --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> @@ -30,28 +30,6 @@
> 
>  #include "mx28_init.h"
> 
> -void mx28_power_clock2xtal(void)
> -{
> -	struct mx28_clkctrl_regs *clkctrl_regs =
> -		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
> -
> -	/* Set XTAL as CPU reference clock */
> -	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
> -		&clkctrl_regs->hw_clkctrl_clkseq_set);
> -}
> -
> -void mx28_power_clock2pll(void)
> -{
> -	struct mx28_clkctrl_regs *clkctrl_regs =
> -		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
> -
> -	writel(CLKCTRL_PLL0CTRL0_POWER,
> -		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
> -	early_delay(100);
> -	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
> -		&clkctrl_regs->hw_clkctrl_clkseq_clr);
> -}
> -
>  void mx28_power_clear_auto_restart(void)
>  {
>  	struct mx28_rtc_regs *rtc_regs =
> @@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)
>  	mx28_src_power_init();
> 
>  	mx28_5v_boot();
> -	mx28_power_clock2pll();
> 
>  	mx28_init_batt_bo();
>  	mx28_switch_vddd_to_dcdc_source();
> @@ -880,7 +857,6 @@ void mx28_power_init(void)
>  	struct mx28_power_regs *power_regs =
>  		(struct mx28_power_regs *)MXS_POWER_BASE;
> 
> -	mx28_power_clock2xtal();
>  	mx28_power_clear_auto_restart();
>  	mx28_power_set_linreg();
>  	mx28_power_setup_5v_detect();

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Fabio Estevam]

On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
>> From: Robert Delien <robert@delien.nl>
>>
>> This patch prevents the needless switching on and off of PLL bypass
>> mode. With this patch in place, single-stepping through the SPL is
>> now possible.
>
> Why did FSL have it in the bootlets though? Fabio, can you explain?

Let me ask around and see what I can find about it.

Regards,

Fabio Estevam

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Marek Vasut]

> From: Robert Delien <robert@delien.nl>
> 
> This set of patches fixes ref_cpu clock setup.
> 
> Robert Delien (4):
>   Renamed mx28_register to mx28_register_32 to prepare for
>     mx28_register_8
>   Introducing 8-bit wide register, mx28_register_8
>   Fix erroneous 32-bit access to hw_clkctrl_frac0 and
>     hw_clkctrl_frac1 registers
>   Preventing needless switching on and off PLL bypass mode,
>     allowing allow single-stepping through the SPL
> 
>  arch/arm/cpu/arm926ejs/mx28/clock.c           |    4 +-
>  arch/arm/cpu/arm926ejs/mx28/iomux.c           |    6 +-
>  arch/arm/cpu/arm926ejs/mx28/mx28.c            |    6 +-
>  arch/arm/include/asm/arch-mx28/regs-apbh.h    |  254
> ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h     |  
> 42 ++--
>  arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   58 +++---
>  arch/arm/include/asm/arch-mx28/regs-common.h  |   12 +-
>  arch/arm/include/asm/arch-mx28/regs-gpmi.h    |   26 ++--
>  arch/arm/include/asm/arch-mx28/regs-i2c.h     |   28 ++--
>  arch/arm/include/asm/arch-mx28/regs-ocotp.h   |   86 ++++----
>  arch/arm/include/asm/arch-mx28/regs-pinctrl.h |  168 ++++++++--------
>  arch/arm/include/asm/arch-mx28/regs-power.h   |   28 ++--
>  arch/arm/include/asm/arch-mx28/regs-rtc.h     |   28 ++--
>  arch/arm/include/asm/arch-mx28/regs-ssp.h     |   40 ++--
>  arch/arm/include/asm/arch-mx28/regs-timrot.h  |   38 ++--
>  arch/arm/include/asm/arch-mx28/regs-usbphy.h  |   20 +-
>  arch/arm/include/asm/arch-mx28/sys_proto.h    |   10 +-
>  drivers/gpio/mxs_gpio.c                       |   16 +-
>  drivers/usb/host/ehci-mxs.c                   |    8 +-
>  19 files changed, 441 insertions(+), 437 deletions(-)

Robert, I tested first three patches on my board and it refuses to boot. Why?

M

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Robert Deliën]

> Robert, I tested first three patches on my board and it refuses to boot. Why?

I'm trying to reproduce, but my workspace no longer builds after a pull... The set
obviously works in my own workspace, so I'm trying to figure out the problem.

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Robert Deliën]

> Robert, I tested first three patches on my board and it refuses to boot. Why?

I can reproduce now. It all goes south after patch 3. I'm working on it.

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Marek Vasut]

> > Robert, I tested first three patches on my board and it refuses to boot.
> > Why?
> 
> I can reproduce now. It all goes south after patch 3. I'm working on it.

Did you even test before submitting? Also, I think if I remove patch 3, it all 
works fine.

M

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Fabio Estevam]

Hi Marek,

On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
>> From: Robert Delien <robert@delien.nl>
>>
>> This patch prevents the needless switching on and off of PLL bypass
>> mode. With this patch in place, single-stepping through the SPL is
>> now possible.
>
> Why did FSL have it in the bootlets though? Fabio, can you explain?

Anson (in Cc) explained the following:

"The switch of CPU clock is to make our EVK board can boot up the
uboot and kernel with less than 100mA power consumption to meet the
USB specification, because there is chance that the EVK board is power
by USB cable only, we need to make sure in this scenario, before USB
enum done, the total power consumption for our EVK board should be
less than 100mA, but if CPU running with PLL on, the power consumption
is > 100mA under uboot, so we need to disable PLL and switch CPU clock
to XTAL before USB enum done."

Regards,

Fabio Estevam

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Marek Vasut]

> Hi Marek,
> 
> On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
> >> From: Robert Delien <robert@delien.nl>
> >> 
> >> This patch prevents the needless switching on and off of PLL bypass
> >> mode. With this patch in place, single-stepping through the SPL is
> >> now possible.
> > 
> > Why did FSL have it in the bootlets though? Fabio, can you explain?
> 
> Anson (in Cc) explained the following:
> 
> "The switch of CPU clock is to make our EVK board can boot up the
> uboot and kernel with less than 100mA power consumption to meet the
> USB specification, because there is chance that the EVK board is power
> by USB cable only, we need to make sure in this scenario, before USB
> enum done, the total power consumption for our EVK board should be
> less than 100mA, but if CPU running with PLL on, the power consumption
> is > 100mA under uboot, so we need to disable PLL and switch CPU clock
> to XTAL before USB enum done."
> 

And by running off XTAL, the consumption grows so dramatically?

M

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Marek Vasut]

> That is because not only CPU running @ PLL, HBUS also source from P_CLK, we
> switch CPU clock to XTAL, the HBUS clock also slow down.

Ok, but you switch it back to PLL after the power supply was configured. And 
then the consumption grows back.

M
> 
> Best Regards.
> Anson huang ???
>  
> Freescale Semiconductor Shanghai
> ?????????192?C?2?
> 201203
> Tel:021-28937058
> 
> $-----Original Message-----
> $From: Marek Vasut [mailto:marek.vasut at gmail.com]
> $Sent: Wednesday, February 08, 2012 10:43 AM
> $To: Fabio Estevam
> $Cc: Huang Yongcai-B20788; robert at delien.nl; u-boot at lists.denx.de
> $Subject: Re: [PATCH 4/4 v4] Preventing needless switching on and off PLL
> bypass $mode, allowing allow single-stepping through the SPL
> $
> $> Hi Marek,
> $>
> $> On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com>
> wrote: $> >> From: Robert Delien <robert@delien.nl>
> $> >>
> $> >> This patch prevents the needless switching on and off of PLL bypass
> $> >> mode. With this patch in place, single-stepping through the SPL is
> $> >> now possible.
> $> >
> $> > Why did FSL have it in the bootlets though? Fabio, can you explain?
> $>
> $> Anson (in Cc) explained the following:
> $>
> $> "The switch of CPU clock is to make our EVK board can boot up the
> $> uboot and kernel with less than 100mA power consumption to meet the
> $> USB specification, because there is chance that the EVK board is power
> $> by USB cable only, we need to make sure in this scenario, before USB
> $> enum done, the total power consumption for our EVK board should be
> $> less than 100mA, but if CPU running with PLL on, the power consumption
> $> is > 100mA under uboot, so we need to disable PLL and switch CPU clock
> $> to XTAL before USB enum done."
> $>
> $
> $And by running off XTAL, the consumption grows so dramatically?
> $
> $M

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Robert Deliën]

> Did you even test before submitting? Also, I think if I remove patch 3, it all
> works fine.

Naturally, I did. Yet on my own SVN controlled workspace, because my
GIT workspace of the mainline didn't build yesterday.

I'm looking at the differences now, and there aren't any concerning i.mx28.
But we're going on...

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> "The switch of CPU clock is to make our EVK board can boot up the
> uboot and kernel with less than 100mA power consumption to meet the
> USB specification

That's actually a very good point. For that scenario we may even consider
to use the SoC's internal 24MHz ring oscillator instead of the crystal.

But this also means that we should disable bypass mode either a whole lot
later, or make it depend on CONFIG_USB.

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> And by running off XTAL, the consumption grows so dramatically?

No, switching on the PLL does.

And the PLL can use either the external XTAL or the internal ring-
oscillator as a reference. The external XTAL is very accurate, but
uses power. The ring-oscillator is not very accurate, but very
energy efficient.

On the EVK, the external XTAL cannot be powered down
separately, so if it's consuming power anyway, there\s not reason
not to use it over the ring-oscillator. But a more generic design
may want use ring-oscillator initially.

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> That is because not only CPU running @ PLL, HBUS also source from P_CLK, we switch
> CPU clock to XTAL, the HBUS clock also slow down.

You're right, but I'm not switching back to XTAL. I'm just postponing the switch to PLL. Not
in the last reason because the first switch to PLL is incorrect (and shouldn't even work).

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> Ok, but you switch it back to PLL after the power supply was configured. And
> then the consumption grows back.

Yes, power_init switches to PLL (yet incorrectly). And memory_init switches back
to XTAL when configuring hbus for a brief moment, to switch to PLL after hbus
is configured. My proposal is to leave out the incorrect first switch, and leave it
on XTAL until hbus is configured. Thhough is still doesn't take care the <100mA
requirement mentioned by Fabio...

[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> 1. Switch P_CLK to XTAL;
> 2. Check power source, if there is battery available, we switch back to PLL and make CPU running @ full
>  speed, and power is sourced from battery;
> 3. If battery is not available, and the power supply is from USB host, then we let CPU running @ XTAL
> until booting up kernel and USB driver enum done, then switch to PLL.

I fully agree.

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Marek Vasut]

> > Did you even test before submitting? Also, I think if I remove patch 3,
> > it all works fine.
> 
> Naturally, I did. Yet on my own SVN controlled workspace, because my
> GIT workspace of the mainline didn't build yesterday.
> 
> I'm looking at the differences now, and there aren't any concerning i.mx28.
> But we're going on...

Should be fixed now (look for tbclk in u-boot mailing list) ... there's a patch

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Robert Deliën]

> Robert, I tested first three patches on my board and it refuses to boot. Why?

The problem is in here:
io_reg = MXC_IOCLK1 - io; /* Register order is reversed */

I will rework and resubmit the patches 'soon'. I'm a bit numb of reworking and resubmitting and I just received a board to bringup last week, and that's got my priority.

BTW: It seems that mx28evk DDR2 is overclocked a bit. For example tRCD is set to 3, where it should be. I didn't look into all the other settings yet, because lowering the clock helps for my board, for now.

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Marek Vasut]

> > Robert, I tested first three patches on my board and it refuses to boot.
> > Why?
> 
> The problem is in here:
> io_reg = MXC_IOCLK1 - io; /* Register order is reversed */
> 
> I will rework and resubmit the patches 'soon'. I'm a bit numb of reworking
> and resubmitting and I just received a board to bringup last week, and
> that's got my priority.

git rebase -i HEAD~3

(if you have the patch you want to rework 3 patches deep)

Change "pick" to the left of the patch to "edit"

Do the change in the file.

git add <file>

git rebase --continue

<submit>

> 
> BTW: It seems that mx28evk DDR2 is overclocked a bit. For example tRCD is
> set to 3, where it should be. I didn't look into all the other settings
> yet, because lowering the clock helps for my board, for now.

Lowering the clock to what ? I was pondering about this too, the settings in 
spl_mem_init are for DENX m28 board, so maybe someone should abstract that out.

M

[U-Boot] [PATCH] i.MX28: Fix ref_cpu clock setup

[Robert Deliën]

Hi Marek,

> git rebase -i HEAD~3
> (if you have the patch you want to rework 3 patches deep)
> Change "pick" to the left of the patch to "edit"
> Do the change in the file.
> git add <file>
> git rebase --continue
> <submit>

May be tonight, at my hotel room.

> Lowering the clock to what ?

Down to 137MHz works for me. That's way too low, but at least it keeps my board
going.
But there's nothing wrong with a frequency of 206MHz, as configured currently; We
just should up the CAS to RAS delay to 5 cycles, from the 3 configured currently.
Perhaps others parameters need a little attention too, but there are so many registers
for DDR to check here...

> I was pondering about this too, the settings in
> spl_mem_init are for DENX m28 board, so maybe someone should abstract that out.

I'm not happy with it either, but the way it is now seems to be the most common one.
And due to the huge amount of registers, I doubt if it could be abstracted nicely,
without turning it into an even bigger mess. I'm afraid there's little alternatives to tuning
DDR parameters for each board separately.

Cheers,

        Robert.