[U-Boot] [PATCH v2 0/2] usb/mx6q: USB EHCI support for MX6Q boards

[U-Boot] [PATCH v2 0/2] usb/mx6q: USB EHCI support for MX6Q boards

[Wolfgang Grandegger]

v1 was bad, sorry. v2 fixes various issues reported by Dirk and Fabio.
The patches are based on head of Stefano's "u-boot-imx" tree.

Wolfgang

Wolfgang Grandegger (2):
  usb/ehci: Add USB support for the MX6Q
  mx6qsabrelite: add and enable USB Host 1 support

 arch/arm/cpu/armv7/mx6/clock.c                |   13 ++
 arch/arm/include/asm/arch-mx6/clock.h         |    1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h      |    3 +
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   18 +++
 drivers/usb/host/Makefile                     |    1 +
 drivers/usb/host/ehci-mx6.c                   |  205 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++
 7 files changed, 254 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/host/ehci-mx6.c

-- 
1.7.7.6

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Wolfgang Grandegger]

Currently, only USB Host 1 is supported.

Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 arch/arm/cpu/armv7/mx6/clock.c           |   13 ++
 arch/arm/include/asm/arch-mx6/clock.h    |    1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h |    3 +
 drivers/usb/host/Makefile                |    1 +
 drivers/usb/host/ehci-mx6.c              |  205 ++++++++++++++++++++++++++++++
 5 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/host/ehci-mx6.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fa3a124..ef98563 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -36,6 +36,19 @@ enum pll_clocks {
 
 struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
 
+void enable_usboh3_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR6);
+	if (enable)
+		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+	else
+		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+	__raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
 	u32 div;
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 636458f..613809b 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -46,5 +46,6 @@ enum mxc_clock {
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_usboh3_clk(unsigned char enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3b5fd25..2bfe891 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -111,6 +111,9 @@
 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 77e217f..1b62cc2 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -43,6 +43,7 @@ endif
 COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
+COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
 COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
new file mode 100644
index 0000000..b7bf49d
--- /dev/null
+++ b/drivers/usb/host/ehci-mx6.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <usb/ehci-fsl.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/iomux-v3.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#define USB_OTGREGS_OFFSET	0x000
+#define USB_H1REGS_OFFSET	0x200
+#define USB_H2REGS_OFFSET	0x400
+#define USB_H3REGS_OFFSET	0x600
+#define USB_OTHERREGS_OFFSET	0x800
+
+#define USB_H1_CTRL_OFFSET	0x04
+
+#define USBPHY_CTRL				0x00000030
+#define USBPHY_CTRL_SET				0x00000034
+#define USBPHY_CTRL_CLR				0x00000038
+#define USBPHY_CTRL_TOG				0x0000003c
+
+#define USBPHY_PWD				0x00000000
+#define USBPHY_CTRL_SFTRST			0x80000000
+#define USBPHY_CTRL_CLKGATE			0x40000000
+#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
+#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
+
+#define ANADIG_USB2_CHRG_DETECT			0x00000210
+#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
+#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
+
+#define ANADIG_USB2_PLL_480_CTRL		0x00000020
+#define ANADIG_USB2_PLL_480_CTRL_SET		0x00000024
+#define ANADIG_USB2_PLL_480_CTRL_CLR		0x00000028
+#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
+#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
+#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
+#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
+
+
+#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
+
+/* USBCMD */
+#define UH1_USBCMD_OFFSET	0x140
+#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
+#define UCMD_RESET		(1 << 1) /* controller reset */
+
+static void usbh1_internal_phy_clock_gate(int on)
+{
+	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+
+	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
+	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
+}
+
+static void usbh1_power_config(void)
+{
+	void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
+
+	/*
+	 * Some phy and power's special controls for host1
+	 * 1. The external charger detector needs to be disabled
+	 * or the signal at DP will be poor
+	 * 2. The PLL's power and output to usb for host 1
+	 * is totally controlled by IC, so the Software only needs
+	 * to enable them@initializtion.
+	 */
+	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+		     anatop_base + ANADIG_USB2_CHRG_DETECT);
+
+	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+		     anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
+
+	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+		     ANADIG_USB2_PLL_480_CTRL_POWER |
+		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
+		     anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
+}
+
+static int usbh1_phy_enable(void)
+{
+	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
+						 USB_H1REGS_OFFSET +
+						 UH1_USBCMD_OFFSET);
+	u32 val;
+
+	/* Stop then Reset */
+	val = __raw_readl(usb_cmd);
+	val &= ~UCMD_RUN_STOP;
+	__raw_writel(val, usb_cmd);
+	while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
+		;
+
+	val = __raw_readl(usb_cmd);
+	val |= UCMD_RESET;
+	__raw_writel(val, usb_cmd);
+	while (__raw_readl(usb_cmd) & UCMD_RESET)
+		;
+
+	/* Reset USBPHY module */
+	val = __raw_readl(phy_ctrl);
+	val |= USBPHY_CTRL_SFTRST;
+	__raw_writel(val, phy_ctrl);
+	udelay(10);
+
+	/* Remove CLKGATE and SFTRST */
+	val = __raw_readl(phy_ctrl);
+	val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
+	__raw_writel(val, phy_ctrl);
+	udelay(10);
+
+	/* Power up the PHY */
+	__raw_writel(0, phy_reg + USBPHY_PWD);
+	/* enable FS/LS device */
+	val = __raw_readl(phy_reg + USBPHY_CTRL);
+	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
+	__raw_writel(val, phy_reg + USBPHY_CTRL);
+
+	return 0;
+}
+
+static void usbh1_oc_config(void)
+{
+	void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
+	void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
+	u32 val;
+
+	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
+	/* mx6qarm2 seems to required a different setting*/
+	val &= ~UCTRL_OVER_CUR_POL;
+#else
+	val |= UCTRL_OVER_CUR_POL;
+#endif
+	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+
+	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+	val |= UCTRL_OVER_CUR_DIS;
+	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+
+	enable_usboh3_clk(1);
+	mdelay(1);
+
+	/* Do board specific initialization */
+	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
+
+#if CONFIG_MXC_USB_PORT == 1
+	/* USB Host 1 */
+	usbh1_power_config();
+	usbh1_oc_config();
+	usbh1_internal_phy_clock_gate(1);
+	usbh1_phy_enable();
+#else
+#error "MXC USB port not yet supported"
+#endif
+
+	ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+		(0x200 * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t)hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+
+	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+	setbits_le32(&ehci->portsc, USB_EN);
+
+	mdelay(10);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
-- 
1.7.7.6

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> Currently, only USB Host 1 is supported.

Hi,

this resembles mx28 USBH ... or am I wrong? Can't these be coalesced together?

btw Fabio, do we support mx6q USB host in mainline Linux ?

> 
> Cc: Remy Bohmer <linux@bohmer.net>
> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
> ---
>  arch/arm/cpu/armv7/mx6/clock.c           |   13 ++
>  arch/arm/include/asm/arch-mx6/clock.h    |    1 +
>  arch/arm/include/asm/arch-mx6/imx-regs.h |    3 +
>  drivers/usb/host/Makefile                |    1 +
>  drivers/usb/host/ehci-mx6.c              |  205
> ++++++++++++++++++++++++++++++ 5 files changed, 223 insertions(+), 0
> deletions(-)
>  create mode 100644 drivers/usb/host/ehci-mx6.c
> 
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c
> b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124..ef98563 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -36,6 +36,19 @@ enum pll_clocks {
> 
>  struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> 
> +void enable_usboh3_clk(unsigned char enable)
> +{
> +	u32 reg;
> +
> +	reg = __raw_readl(&imx_ccm->CCGR6);
> +	if (enable)
> +		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
> +	else
> +		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
> +	__raw_writel(reg, &imx_ccm->CCGR6);
> +
> +}
> +
>  static u32 decode_pll(enum pll_clocks pll, u32 infreq)
>  {
>  	u32 div;
> diff --git a/arch/arm/include/asm/arch-mx6/clock.h
> b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644
> --- a/arch/arm/include/asm/arch-mx6/clock.h
> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -46,5 +46,6 @@ enum mxc_clock {
>  u32 imx_get_uartclk(void);
>  u32 imx_get_fecclk(void);
>  unsigned int mxc_get_clock(enum mxc_clock clk);
> +void enable_usboh3_clk(unsigned char enable);
> 
>  #endif /* __ASM_ARCH_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3b5fd25..2bfe891 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -111,6 +111,9 @@
>  #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
>  #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
>  #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
> +#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
> +#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
> +#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
>  #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
>  #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
>  #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 77e217f..1b62cc2 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -43,6 +43,7 @@ endif
>  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
>  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
>  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
> +COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
>  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
>  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
>  COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> new file mode 100644
> index 0000000..b7bf49d
> --- /dev/null
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -0,0 +1,205 @@
> +/*
> + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License + * for more details.
> + */
> +
> +#include <common.h>
> +#include <usb.h>
> +#include <errno.h>
> +#include <linux/compiler.h>
> +#include <usb/ehci-fsl.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/mx6x_pins.h>
> +#include <asm/arch/iomux-v3.h>
> +
> +#include "ehci.h"
> +#include "ehci-core.h"
> +
> +#define USB_OTGREGS_OFFSET	0x000
> +#define USB_H1REGS_OFFSET	0x200
> +#define USB_H2REGS_OFFSET	0x400
> +#define USB_H3REGS_OFFSET	0x600
> +#define USB_OTHERREGS_OFFSET	0x800
> +
> +#define USB_H1_CTRL_OFFSET	0x04
> +
> +#define USBPHY_CTRL				0x00000030
> +#define USBPHY_CTRL_SET				0x00000034
> +#define USBPHY_CTRL_CLR				0x00000038
> +#define USBPHY_CTRL_TOG				0x0000003c
> +
> +#define USBPHY_PWD				0x00000000
> +#define USBPHY_CTRL_SFTRST			0x80000000
> +#define USBPHY_CTRL_CLKGATE			0x40000000
> +#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
> +#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
> +
> +#define ANADIG_USB2_CHRG_DETECT			0x00000210
> +#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
> +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
> +
> +#define ANADIG_USB2_PLL_480_CTRL		0x00000020
> +#define ANADIG_USB2_PLL_480_CTRL_SET		0x00000024
> +#define ANADIG_USB2_PLL_480_CTRL_CLR		0x00000028
> +#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
> +#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
> +#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
> +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
> +
> +
> +#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
> +#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection
> */ +
> +/* USBCMD */
> +#define UH1_USBCMD_OFFSET	0x140
> +#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
> +#define UCMD_RESET		(1 << 1) /* controller reset */
> +
> +static void usbh1_internal_phy_clock_gate(int on)
> +{
> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> +
> +	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
> +	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
> +}
> +
> +static void usbh1_power_config(void)
> +{
> +	void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
> +
> +	/*
> +	 * Some phy and power's special controls for host1
> +	 * 1. The external charger detector needs to be disabled
> +	 * or the signal at DP will be poor
> +	 * 2. The PLL's power and output to usb for host 1
> +	 * is totally controlled by IC, so the Software only needs
> +	 * to enable them at initializtion.
> +	 */
> +	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
> +		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
> +		     anatop_base + ANADIG_USB2_CHRG_DETECT);
> +
> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
> +
> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
> +		     ANADIG_USB2_PLL_480_CTRL_POWER |
> +		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);

This part looks mx28ish

> +}
> +
> +static int usbh1_phy_enable(void)
> +{
> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> +	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
> +	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
> +						 USB_H1REGS_OFFSET +
> +						 UH1_USBCMD_OFFSET);
> +	u32 val;
> +
> +	/* Stop then Reset */
> +	val = __raw_readl(usb_cmd);
> +	val &= ~UCMD_RUN_STOP;
> +	__raw_writel(val, usb_cmd);
> +	while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
> +		;
> +
> +	val = __raw_readl(usb_cmd);
> +	val |= UCMD_RESET;
> +	__raw_writel(val, usb_cmd);
> +	while (__raw_readl(usb_cmd) & UCMD_RESET)
> +		;
> +
> +	/* Reset USBPHY module */
> +	val = __raw_readl(phy_ctrl);
> +	val |= USBPHY_CTRL_SFTRST;
> +	__raw_writel(val, phy_ctrl);
> +	udelay(10);

This part too.

> +
> +	/* Remove CLKGATE and SFTRST */
> +	val = __raw_readl(phy_ctrl);
> +	val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
> +	__raw_writel(val, phy_ctrl);
> +	udelay(10);

This too, looks like mx28_reset_block(). But maybe I'm just paranoid and spooky 
here :)

> +
> +	/* Power up the PHY */
> +	__raw_writel(0, phy_reg + USBPHY_PWD);
> +	/* enable FS/LS device */
> +	val = __raw_readl(phy_reg + USBPHY_CTRL);
> +	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
> +	__raw_writel(val, phy_reg + USBPHY_CTRL);

And maybe not ... this looks like MX28 phy interface.

M

> +
> +	return 0;
> +}
> +
> +static void usbh1_oc_config(void)
> +{
> +	void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
> +	void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
> +	u32 val;
> +
> +	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
> +#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
> +	/* mx6qarm2 seems to required a different setting*/
> +	val &= ~UCTRL_OVER_CUR_POL;
> +#else
> +	val |= UCTRL_OVER_CUR_POL;
> +#endif
> +	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
> +
> +	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
> +	val |= UCTRL_OVER_CUR_DIS;
> +	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
> +}
> +
> +int ehci_hcd_init(void)
> +{
> +	struct usb_ehci *ehci;
> +
> +	enable_usboh3_clk(1);
> +	mdelay(1);
> +
> +	/* Do board specific initialization */
> +	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
> +
> +#if CONFIG_MXC_USB_PORT == 1
> +	/* USB Host 1 */
> +	usbh1_power_config();
> +	usbh1_oc_config();
> +	usbh1_internal_phy_clock_gate(1);
> +	usbh1_phy_enable();
> +#else
> +#error "MXC USB port not yet supported"
> +#endif
> +
> +	ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
> +		(0x200 * CONFIG_MXC_USB_PORT));
> +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +	hcor = (struct ehci_hcor *)((uint32_t)hccr +
> +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +	setbits_le32(&ehci->usbmode, CM_HOST);
> +
> +	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
> +	setbits_le32(&ehci->portsc, USB_EN);
> +
> +	mdelay(10);
> +
> +	return 0;
> +}
> +
> +int ehci_hcd_stop(void)
> +{
> +	return 0;
> +}

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> > Currently, only USB Host 1 is supported.
> 
> Hi,
> 
> this resembles mx28 USBH ... or am I wrong? Can't these be coalesced
> together?
> 
> btw Fabio, do we support mx6q USB host in mainline Linux ?

To make this even creepier ... the mx6q GPMI NAND interface is also taken from 
mx28.

So basically, MX6q is MX28 with more (and v7) cores?

M

> 
> > Cc: Remy Bohmer <linux@bohmer.net>
> > Signed-off-by: Wolfgang Grandegger <wg@denx.de>
> > ---
> > 
> >  arch/arm/cpu/armv7/mx6/clock.c           |   13 ++
> >  arch/arm/include/asm/arch-mx6/clock.h    |    1 +
> >  arch/arm/include/asm/arch-mx6/imx-regs.h |    3 +
> >  drivers/usb/host/Makefile                |    1 +
> >  drivers/usb/host/ehci-mx6.c              |  205
> > 
> > ++++++++++++++++++++++++++++++ 5 files changed, 223 insertions(+), 0
> > deletions(-)
> > 
> >  create mode 100644 drivers/usb/host/ehci-mx6.c
> > 
> > diff --git a/arch/arm/cpu/armv7/mx6/clock.c
> > b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124..ef98563 100644
> > --- a/arch/arm/cpu/armv7/mx6/clock.c
> > +++ b/arch/arm/cpu/armv7/mx6/clock.c
> > @@ -36,6 +36,19 @@ enum pll_clocks {
> > 
> >  struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> > 
> > +void enable_usboh3_clk(unsigned char enable)
> > +{
> > +	u32 reg;
> > +
> > +	reg = __raw_readl(&imx_ccm->CCGR6);
> > +	if (enable)
> > +		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
> > +	else
> > +		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
> > +	__raw_writel(reg, &imx_ccm->CCGR6);
> > +
> > +}
> > +
> > 
> >  static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> >  {
> >  
> >  	u32 div;
> > 
> > diff --git a/arch/arm/include/asm/arch-mx6/clock.h
> > b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644
> > --- a/arch/arm/include/asm/arch-mx6/clock.h
> > +++ b/arch/arm/include/asm/arch-mx6/clock.h
> > @@ -46,5 +46,6 @@ enum mxc_clock {
> > 
> >  u32 imx_get_uartclk(void);
> >  u32 imx_get_fecclk(void);
> >  unsigned int mxc_get_clock(enum mxc_clock clk);
> > 
> > +void enable_usboh3_clk(unsigned char enable);
> > 
> >  #endif /* __ASM_ARCH_CLOCK_H */
> > 
> > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> > b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3b5fd25..2bfe891 100644
> > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> > @@ -111,6 +111,9 @@
> > 
> >  #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
> >  #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
> >  #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
> > 
> > +#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
> > +#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
> > +#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
> > 
> >  #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
> >  #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
> >  #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
> > 
> > diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> > index 77e217f..1b62cc2 100644
> > --- a/drivers/usb/host/Makefile
> > +++ b/drivers/usb/host/Makefile
> > @@ -43,6 +43,7 @@ endif
> > 
> >  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
> >  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
> >  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
> > 
> > +COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
> > 
> >  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
> >  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
> >  COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
> > 
> > diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> > new file mode 100644
> > index 0000000..b7bf49d
> > --- /dev/null
> > +++ b/drivers/usb/host/ehci-mx6.c
> > @@ -0,0 +1,205 @@
> > +/*
> > + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
> > + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > it + * under the terms of the GNU General Public License as published by
> > the + * Free Software Foundation; either version 2 of the License, or
> > (at your + * option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > + * WITHOUT ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License + * for more details.
> > + */
> > +
> > +#include <common.h>
> > +#include <usb.h>
> > +#include <errno.h>
> > +#include <linux/compiler.h>
> > +#include <usb/ehci-fsl.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/imx-regs.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/mx6x_pins.h>
> > +#include <asm/arch/iomux-v3.h>
> > +
> > +#include "ehci.h"
> > +#include "ehci-core.h"
> > +
> > +#define USB_OTGREGS_OFFSET	0x000
> > +#define USB_H1REGS_OFFSET	0x200
> > +#define USB_H2REGS_OFFSET	0x400
> > +#define USB_H3REGS_OFFSET	0x600
> > +#define USB_OTHERREGS_OFFSET	0x800
> > +
> > +#define USB_H1_CTRL_OFFSET	0x04
> > +
> > +#define USBPHY_CTRL				0x00000030
> > +#define USBPHY_CTRL_SET				0x00000034
> > +#define USBPHY_CTRL_CLR				0x00000038
> > +#define USBPHY_CTRL_TOG				0x0000003c
> > +
> > +#define USBPHY_PWD				0x00000000
> > +#define USBPHY_CTRL_SFTRST			0x80000000
> > +#define USBPHY_CTRL_CLKGATE			0x40000000
> > +#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
> > +#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
> > +
> > +#define ANADIG_USB2_CHRG_DETECT			0x00000210
> > +#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
> > +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
> > +
> > +#define ANADIG_USB2_PLL_480_CTRL		0x00000020
> > +#define ANADIG_USB2_PLL_480_CTRL_SET		0x00000024
> > +#define ANADIG_USB2_PLL_480_CTRL_CLR		0x00000028
> > +#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
> > +#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
> > +#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
> > +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
> > +
> > +
> > +#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
> > +#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection
> > */ +
> > +/* USBCMD */
> > +#define UH1_USBCMD_OFFSET	0x140
> > +#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
> > +#define UCMD_RESET		(1 << 1) /* controller reset */
> > +
> > +static void usbh1_internal_phy_clock_gate(int on)
> > +{
> > +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> > +
> > +	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
> > +	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
> > +}
> > +
> > +static void usbh1_power_config(void)
> > +{
> > +	void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
> > +
> > +	/*
> > +	 * Some phy and power's special controls for host1
> > +	 * 1. The external charger detector needs to be disabled
> > +	 * or the signal at DP will be poor
> > +	 * 2. The PLL's power and output to usb for host 1
> > +	 * is totally controlled by IC, so the Software only needs
> > +	 * to enable them at initializtion.
> > +	 */
> > +	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
> > +		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
> > +		     anatop_base + ANADIG_USB2_CHRG_DETECT);
> > +
> > +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
> > +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
> > +
> > +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
> > +		     ANADIG_USB2_PLL_480_CTRL_POWER |
> > +		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
> > +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
> 
> This part looks mx28ish
> 
> > +}
> > +
> > +static int usbh1_phy_enable(void)
> > +{
> > +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> > +	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
> > +	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
> > +						 USB_H1REGS_OFFSET +
> > +						 UH1_USBCMD_OFFSET);
> > +	u32 val;
> > +
> > +	/* Stop then Reset */
> > +	val = __raw_readl(usb_cmd);
> > +	val &= ~UCMD_RUN_STOP;
> > +	__raw_writel(val, usb_cmd);
> > +	while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
> > +		;
> > +
> > +	val = __raw_readl(usb_cmd);
> > +	val |= UCMD_RESET;
> > +	__raw_writel(val, usb_cmd);
> > +	while (__raw_readl(usb_cmd) & UCMD_RESET)
> > +		;
> > +
> > +	/* Reset USBPHY module */
> > +	val = __raw_readl(phy_ctrl);
> > +	val |= USBPHY_CTRL_SFTRST;
> > +	__raw_writel(val, phy_ctrl);
> > +	udelay(10);
> 
> This part too.
> 
> > +
> > +	/* Remove CLKGATE and SFTRST */
> > +	val = __raw_readl(phy_ctrl);
> > +	val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
> > +	__raw_writel(val, phy_ctrl);
> > +	udelay(10);
> 
> This too, looks like mx28_reset_block(). But maybe I'm just paranoid and
> spooky here :)
> 
> > +
> > +	/* Power up the PHY */
> > +	__raw_writel(0, phy_reg + USBPHY_PWD);
> > +	/* enable FS/LS device */
> > +	val = __raw_readl(phy_reg + USBPHY_CTRL);
> > +	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
> > +	__raw_writel(val, phy_reg + USBPHY_CTRL);
> 
> And maybe not ... this looks like MX28 phy interface.
> 
> M
> 
> > +
> > +	return 0;
> > +}
> > +
> > +static void usbh1_oc_config(void)
> > +{
> > +	void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
> > +	void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
> > +	u32 val;
> > +
> > +	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
> > +#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
> > +	/* mx6qarm2 seems to required a different setting*/
> > +	val &= ~UCTRL_OVER_CUR_POL;
> > +#else
> > +	val |= UCTRL_OVER_CUR_POL;
> > +#endif
> > +	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
> > +
> > +	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
> > +	val |= UCTRL_OVER_CUR_DIS;
> > +	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
> > +}
> > +
> > +int ehci_hcd_init(void)
> > +{
> > +	struct usb_ehci *ehci;
> > +
> > +	enable_usboh3_clk(1);
> > +	mdelay(1);
> > +
> > +	/* Do board specific initialization */
> > +	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
> > +
> > +#if CONFIG_MXC_USB_PORT == 1
> > +	/* USB Host 1 */
> > +	usbh1_power_config();
> > +	usbh1_oc_config();
> > +	usbh1_internal_phy_clock_gate(1);
> > +	usbh1_phy_enable();
> > +#else
> > +#error "MXC USB port not yet supported"
> > +#endif
> > +
> > +	ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
> > +		(0x200 * CONFIG_MXC_USB_PORT));
> > +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> > +	hcor = (struct ehci_hcor *)((uint32_t)hccr +
> > +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> > +	setbits_le32(&ehci->usbmode, CM_HOST);
> > +
> > +	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
> > +	setbits_le32(&ehci->portsc, USB_EN);
> > +
> > +	mdelay(10);
> > +
> > +	return 0;
> > +}
> > +
> > +int ehci_hcd_stop(void)
> > +{
> > +	return 0;
> > +}

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Fabio Estevam]

On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut <marek.vasut@gmail.com> wrote:

> btw Fabio, do we support mx6q USB host in mainline Linux ?

Not yet, Marek.

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Dirk Behme]

On 11.02.2012 19:46, Fabio Estevam wrote:
> On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>  wrote:
>
>> btw Fabio, do we support mx6q USB host in mainline Linux ?
>
> Not yet, Marek.

Linaro has it working with

http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=de941f9ac0b59c34053618e90e3c1f1d8b5a2d22

http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=4026cfa27332f2e53cfbf72cc98cf4db8c2f2127

It shouldn't be that hard to apply these to plain mainline Linux (?).

Best regards

Dirk

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> On 11.02.2012 19:46, Fabio Estevam wrote:
> > On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>  wrote:
> >> btw Fabio, do we support mx6q USB host in mainline Linux ?
> > 
> > Not yet, Marek.
> 
> Linaro has it working with
> 
> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=de
> 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
> 
> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=40
> 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
> 
> It shouldn't be that hard to apply these to plain mainline Linux (?).

Do you believe this will be accepted into mainline Linux if basically the same 
stuff, except for mx28 did NOT get accepted? The shape of the code was almost 
identical, maybe better. Actually, even the file names are the same here and in 
the old FSL BSP for mx28.

M

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Shilpa Budhihal]

Atleast could that driver be enabled by any means? Please let me know if any such procedure is der to enable the driver. I'm very much confused as to start with it.

Thanks and Regards,
Shilpa
________________________________________
From: u-boot-bounces@lists.denx.de [u-boot-bounces at lists.denx.de] on behalf of Marek Vasut [marek.vasut at gmail.com]
Sent: 12 February, 2012 2:16 PM
To: Dirk Behme
Cc: Fabio Estevam; u-boot at lists.denx.de; Wolfgang Grandegger
Subject: Re: [U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

> On 11.02.2012 19:46, Fabio Estevam wrote:
> > On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>  wrote:
> >> btw Fabio, do we support mx6q USB host in mainline Linux ?
> >
> > Not yet, Marek.
>
> Linaro has it working with
>
> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=de
> 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
>
> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=40
> 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
>
> It shouldn't be that hard to apply these to plain mainline Linux (?).

Do you believe this will be accepted into mainline Linux if basically the same
stuff, except for mx28 did NOT get accepted? The shape of the code was almost
identical, maybe better. Actually, even the file names are the same here and in
the old FSL BSP for mx28.

M
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[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> Atleast could that driver be enabled by any means? Please let me know if
> any such procedure is der to enable the driver. I'm very much confused as
> to start with it.

DO NOT TOP-POST!!!

What do you mean by "enabled by any means"?

M

> 
> Thanks and Regards,
> Shilpa
> ________________________________________
> From: u-boot-bounces at lists.denx.de [u-boot-bounces at lists.denx.de] on behalf
> of Marek Vasut [marek.vasut at gmail.com] Sent: 12 February, 2012 2:16 PM
> To: Dirk Behme
> Cc: Fabio Estevam; u-boot at lists.denx.de; Wolfgang Grandegger
> Subject: Re: [U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q
> 
> > On 11.02.2012 19:46, Fabio Estevam wrote:
> > > On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>  
wrote:
> > >> btw Fabio, do we support mx6q USB host in mainline Linux ?
> > > 
> > > Not yet, Marek.
> > 
> > Linaro has it working with
> > 
> > http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=
> > de 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
> > 
> > http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=
> > 40 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
> > 
> > It shouldn't be that hard to apply these to plain mainline Linux (?).
> 
> Do you believe this will be accepted into mainline Linux if basically the
> same stuff, except for mx28 did NOT get accepted? The shape of the code
> was almost identical, maybe better. Actually, even the file names are the
> same here and in the old FSL BSP for mx28.
> 
> M
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 
> ________________________________
> 
> DISCLAIMER:
> 
> This email may contain confidential information and is intended only for
> the use of the specific individual(s) to which it is addressed. If you are
> not the intended recipient of this email, you are hereby notified that any
> unauthorized use, dissemination or copying of this email or the
> information contained in it or attached to it is strictly prohibited. If
> you received this message in error, please immediately notify the sender
> at Infotech or Mail.Admin at infotech-enterprises.com and delete the original
> message.

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> even i'm new to u-boot. So didnt know. And I just asked if the present USB
> driver in u-boot can be enabled for mx23evk board?
> 

DO NOT TOP-POST!!!
DO NOT DROP CC!!!

And to answer your question, if you add support for mx23evk, yes.

M

> 
> Thanks and Regards,
> Shilpa
> ________________________________________
> From: Marek Vasut [marek.vasut at gmail.com]
> Sent: 12 February, 2012 2:27 PM
> To: Shilpa Budhihal
> Cc: Dirk Behme; Fabio Estevam; u-boot at lists.denx.de; Wolfgang Grandegger
> Subject: Re: [U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q
> 
> > Atleast could that driver be enabled by any means? Please let me know if
> > any such procedure is der to enable the driver. I'm very much confused as
> > to start with it.
> 
> DO NOT TOP-POST!!!
> 
> What do you mean by "enabled by any means"?
> 
> M
> 
> > Thanks and Regards,
> > Shilpa
> > ________________________________________
> > From: u-boot-bounces at lists.denx.de [u-boot-bounces at lists.denx.de] on
> > behalf of Marek Vasut [marek.vasut at gmail.com] Sent: 12 February, 2012
> > 2:16 PM To: Dirk Behme
> > Cc: Fabio Estevam; u-boot at lists.denx.de; Wolfgang Grandegger
> > Subject: Re: [U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the
> > MX6Q
> > 
> > > On 11.02.2012 19:46, Fabio Estevam wrote:
> > > > On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>
> 
> wrote:
> > > >> btw Fabio, do we support mx6q USB host in mainline Linux ?
> > > > 
> > > > Not yet, Marek.
> > > 
> > > Linaro has it working with
> > > 
> > > http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;
> > > h= de 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
> > > 
> > > http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;
> > > h= 40 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
> > > 
> > > It shouldn't be that hard to apply these to plain mainline Linux (?).
> > 
> > Do you believe this will be accepted into mainline Linux if basically the
> > same stuff, except for mx28 did NOT get accepted? The shape of the code
> > was almost identical, maybe better. Actually, even the file names are the
> > same here and in the old FSL BSP for mx28.
> > 
> > M
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> > 
> > ________________________________
> > 
> > DISCLAIMER:
> > 
> > This email may contain confidential information and is intended only for
> > the use of the specific individual(s) to which it is addressed. If you
> > are not the intended recipient of this email, you are hereby notified
> > that any unauthorized use, dissemination or copying of this email or the
> > information contained in it or attached to it is strictly prohibited. If
> > you received this message in error, please immediately notify the sender
> > at Infotech or Mail.Admin at infotech-enterprises.com and delete the
> > original message.

[U-Boot] i.MX6Q USB host support for mainline Linux (was: Re: [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q)

[Dirk Behme]

While discussing at the U-Boot mailing list about  i.MX6Q USB host 
support for U-Boot, there was the question what's about the same for 
mainline Linux. See below.

I'd like to continue this discussion with a new subject and adding the 
Linaro mailing list.

On 12.02.2012 09:46, Marek Vasut wrote:
>> On 11.02.2012 19:46, Fabio Estevam wrote:
>>> On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>   wrote:
>>>> btw Fabio, do we support mx6q USB host in mainline Linux ?
>>>
>>> Not yet, Marek.
>>
>> Linaro has it working with
>>
>> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=de
>> 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
>>
>> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h=40
>> 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
>>
>> It shouldn't be that hard to apply these to plain mainline Linux (?).
>
> Do you believe this will be accepted into mainline Linux if basically the same
> stuff, except for mx28 did NOT get accepted?

Do you have any pointers to the discussion about this? Hopefully we 
could learn from that.

> The shape of the code was almost
> identical, maybe better. Actually, even the file names are the same here and in
> the old FSL BSP for mx28.

I think the good news is at least that Linaro is working on a more or 
less recent kernel (atm 3.2). So, as mentioned above, porting it from 
the Linaro kernel to the mainline kernel shouldn't be that hard. The 
next step would be to clean them up, hopefully learning from the mx28 
experience mentioned above.

What do you think?

Best regards

Dirk

[U-Boot] i.MX6Q USB host support for mainline Linux (was: Re: [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q)

[Marek Vasut]

> While discussing at the U-Boot mailing list about  i.MX6Q USB host
> support for U-Boot, there was the question what's about the same for
> mainline Linux. See below.
> 
> I'd like to continue this discussion with a new subject and adding the
> Linaro mailing list.

I'm not subscribed, this is gonna make it all a mess.

> 
> On 12.02.2012 09:46, Marek Vasut wrote:
> >> On 11.02.2012 19:46, Fabio Estevam wrote:
> >>> On Sat, Feb 11, 2012 at 5:12 AM, Marek Vasut<marek.vasut@gmail.com>   
wrote:
> >>>> btw Fabio, do we support mx6q USB host in mainline Linux ?
> >>> 
> >>> Not yet, Marek.
> >> 
> >> Linaro has it working with
> >> 
> >> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h
> >> =de 941f9ac0b59c34053618e90e3c1f1d8b5a2d22
> >> 
> >> http://git.linaro.org/gitweb?p=bsp/freescale/linux-linaro.git;a=commit;h
> >> =40 26cfa27332f2e53cfbf72cc98cf4db8c2f2127
> >> 
> >> It shouldn't be that hard to apply these to plain mainline Linux (?).
> > 
> > Do you believe this will be accepted into mainline Linux if basically the
> > same stuff, except for mx28 did NOT get accepted?
> 
> Do you have any pointers to the discussion about this? Hopefully we
> could learn from that.

This is the name of the thread in LAKML:
"RE: Want to Get Suggestion for MX28 USB Submisson"

> 
> > The shape of the code was almost
> > identical, maybe better. Actually, even the file names are the same here
> > and in the old FSL BSP for mx28.
> 
> I think the good news is at least that Linaro is working on a more or
> less recent kernel (atm 3.2). So, as mentioned above, porting it from
> the Linaro kernel to the mainline kernel shouldn't be that hard.

It actually will be, since ... well see the discussion about MX28 USB, it's all 
explained there. Sorry, I'm currently at the verge of falling asleep, very 
tired.

> The
> next step would be to clean them up, hopefully learning from the mx28
> experience mentioned above.

There was something going on about handling the PHY separately from the USB EHCI 
core, that's the part where it got stuck if I recall well.
> 
> What do you think?

I think I'll have a good sleep now, I need it, I'm starting to babble nonsense.
> 
> Best regards
> 
> Dirk

M

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Wolfgang Grandegger]

Hi Marek,

On 02/11/2012 08:12 AM, Marek Vasut wrote:
>> Currently, only USB Host 1 is supported.
> 
> Hi,
> 
> this resembles mx28 USBH ... or am I wrong? Can't these be coalesced together?

Good point. The MX6Q seems to be some kind of clone of the MX28, indeed.
Not only for USB but also for FEC and likely other interfaces as well.

> btw Fabio, do we support mx6q USB host in mainline Linux ?
> 
>>
>> Cc: Remy Bohmer <linux@bohmer.net>
>> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
>> ---
>>  arch/arm/cpu/armv7/mx6/clock.c           |   13 ++
>>  arch/arm/include/asm/arch-mx6/clock.h    |    1 +
>>  arch/arm/include/asm/arch-mx6/imx-regs.h |    3 +
>>  drivers/usb/host/Makefile                |    1 +
>>  drivers/usb/host/ehci-mx6.c              |  205
>> ++++++++++++++++++++++++++++++ 5 files changed, 223 insertions(+), 0
>> deletions(-)
>>  create mode 100644 drivers/usb/host/ehci-mx6.c
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/clock.c
>> b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124..ef98563 100644
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -36,6 +36,19 @@ enum pll_clocks {
>>
>>  struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
>>
>> +void enable_usboh3_clk(unsigned char enable)
>> +{
>> +	u32 reg;
>> +
>> +	reg = __raw_readl(&imx_ccm->CCGR6);
>> +	if (enable)
>> +		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
>> +	else
>> +		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
>> +	__raw_writel(reg, &imx_ccm->CCGR6);
>> +
>> +}
>> +
>>  static u32 decode_pll(enum pll_clocks pll, u32 infreq)
>>  {
>>  	u32 div;
>> diff --git a/arch/arm/include/asm/arch-mx6/clock.h
>> b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644
>> --- a/arch/arm/include/asm/arch-mx6/clock.h
>> +++ b/arch/arm/include/asm/arch-mx6/clock.h
>> @@ -46,5 +46,6 @@ enum mxc_clock {
>>  u32 imx_get_uartclk(void);
>>  u32 imx_get_fecclk(void);
>>  unsigned int mxc_get_clock(enum mxc_clock clk);
>> +void enable_usboh3_clk(unsigned char enable);
>>
>>  #endif /* __ASM_ARCH_CLOCK_H */
>> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3b5fd25..2bfe891 100644
>> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> @@ -111,6 +111,9 @@
>>  #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
>>  #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
>>  #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
>> +#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
>> +#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
>> +#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
>>  #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
>>  #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
>>  #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
>> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
>> index 77e217f..1b62cc2 100644
>> --- a/drivers/usb/host/Makefile
>> +++ b/drivers/usb/host/Makefile
>> @@ -43,6 +43,7 @@ endif
>>  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
>>  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
>>  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
>> +COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
>>  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
>>  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
>>  COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
>> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
>> new file mode 100644
>> index 0000000..b7bf49d
>> --- /dev/null
>> +++ b/drivers/usb/host/ehci-mx6.c
>> @@ -0,0 +1,205 @@
>> +/*
>> + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
>> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> General Public License + * for more details.
>> + */
>> +
>> +#include <common.h>
>> +#include <usb.h>
>> +#include <errno.h>
>> +#include <linux/compiler.h>
>> +#include <usb/ehci-fsl.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/mx6x_pins.h>
>> +#include <asm/arch/iomux-v3.h>
>> +
>> +#include "ehci.h"
>> +#include "ehci-core.h"
>> +
>> +#define USB_OTGREGS_OFFSET	0x000
>> +#define USB_H1REGS_OFFSET	0x200
>> +#define USB_H2REGS_OFFSET	0x400
>> +#define USB_H3REGS_OFFSET	0x600
>> +#define USB_OTHERREGS_OFFSET	0x800
>> +
>> +#define USB_H1_CTRL_OFFSET	0x04
>> +
>> +#define USBPHY_CTRL				0x00000030
>> +#define USBPHY_CTRL_SET				0x00000034
>> +#define USBPHY_CTRL_CLR				0x00000038
>> +#define USBPHY_CTRL_TOG				0x0000003c
>> +
>> +#define USBPHY_PWD				0x00000000
>> +#define USBPHY_CTRL_SFTRST			0x80000000
>> +#define USBPHY_CTRL_CLKGATE			0x40000000
>> +#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
>> +#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000

These macros are already defined in
"arch/arm/include/asm/arch-mx28/regs-usbphy.h".

>> +#define ANADIG_USB2_CHRG_DETECT			0x00000210
>> +#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
>> +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
>> +
>> +#define ANADIG_USB2_PLL_480_CTRL		0x00000020
>> +#define ANADIG_USB2_PLL_480_CTRL_SET		0x00000024
>> +#define ANADIG_USB2_PLL_480_CTRL_CLR		0x00000028
>> +#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
>> +#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
>> +#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
>> +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040

And these are in "arch/arm/include/asm/arch-mx6/ccm_regs.h", which I
just realized after a closer look.

>> +
>> +#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
>> +#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection
>> */ +
>> +/* USBCMD */
>> +#define UH1_USBCMD_OFFSET	0x140
>> +#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
>> +#define UCMD_RESET		(1 << 1) /* controller reset */
>> +
>> +static void usbh1_internal_phy_clock_gate(int on)
>> +{
>> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
>> +
>> +	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
>> +	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
>> +}
>> +
>> +static void usbh1_power_config(void)
>> +{
>> +	void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
>> +
>> +	/*
>> +	 * Some phy and power's special controls for host1
>> +	 * 1. The external charger detector needs to be disabled
>> +	 * or the signal at DP will be poor
>> +	 * 2. The PLL's power and output to usb for host 1
>> +	 * is totally controlled by IC, so the Software only needs
>> +	 * to enable them at initializtion.
>> +	 */
>> +	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
>> +		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
>> +		     anatop_base + ANADIG_USB2_CHRG_DETECT);
>> +
>> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
>> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
>> +
>> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
>> +		     ANADIG_USB2_PLL_480_CTRL_POWER |
>> +		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
>> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
> 
> This part looks mx28ish

Maybe. While searching I realized that the macros and register addresses
are already defined in:

arch/arm/include/asm/arch-mx6/ccm_regs.h

>> +}
>> +
>> +static int usbh1_phy_enable(void)
>> +{
>> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
>> +	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
>> +	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
>> +						 USB_H1REGS_OFFSET +
>> +						 UH1_USBCMD_OFFSET);
>> +	u32 val;
>> +
>> +	/* Stop then Reset */
>> +	val = __raw_readl(usb_cmd);
>> +	val &= ~UCMD_RUN_STOP;
>> +	__raw_writel(val, usb_cmd);
>> +	while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
>> +		;
>> +
>> +	val = __raw_readl(usb_cmd);
>> +	val |= UCMD_RESET;
>> +	__raw_writel(val, usb_cmd);
>> +	while (__raw_readl(usb_cmd) & UCMD_RESET)
>> +		;
>> +
>> +	/* Reset USBPHY module */
>> +	val = __raw_readl(phy_ctrl);
>> +	val |= USBPHY_CTRL_SFTRST;
>> +	__raw_writel(val, phy_ctrl);
>> +	udelay(10);
> 
> This part too.
> 
>> +
>> +	/* Remove CLKGATE and SFTRST */
>> +	val = __raw_readl(phy_ctrl);
>> +	val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
>> +	__raw_writel(val, phy_ctrl);
>> +	udelay(10);
> 
> This too, looks like mx28_reset_block(). But maybe I'm just paranoid and spooky 
> here :)

> 
>> +
>> +	/* Power up the PHY */
>> +	__raw_writel(0, phy_reg + USBPHY_PWD);
>> +	/* enable FS/LS device */
>> +	val = __raw_readl(phy_reg + USBPHY_CTRL);
>> +	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
>> +	__raw_writel(val, phy_reg + USBPHY_CTRL);
> 
> And maybe not ... this looks like MX28 phy interface.

I think MX6 and MX28 could share common register definitions. Note sure
if both will share a lot of code though. To add MX6 USB support to
ehci-mxs.c seems not straight-forward to me, at least. But I will have a
closer look next week...

Wolfgang.

W


Wolfgang.

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Marek Vasut]

> Hi Marek,
> 
> On 02/11/2012 08:12 AM, Marek Vasut wrote:
> >> Currently, only USB Host 1 is supported.
> > 
> > Hi,
> > 
> > this resembles mx28 USBH ... or am I wrong? Can't these be coalesced
> > together?
> 
> Good point. The MX6Q seems to be some kind of clone of the MX28, indeed.
> Not only for USB but also for FEC and likely other interfaces as well.

Yep, USB, NAND, FEC ... maybe something else.

> 
> > btw Fabio, do we support mx6q USB host in mainline Linux ?
> > 
> >> Cc: Remy Bohmer <linux@bohmer.net>
> >> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
> >> ---
> >> 
> >>  arch/arm/cpu/armv7/mx6/clock.c           |   13 ++
> >>  arch/arm/include/asm/arch-mx6/clock.h    |    1 +
> >>  arch/arm/include/asm/arch-mx6/imx-regs.h |    3 +
> >>  drivers/usb/host/Makefile                |    1 +
> >>  drivers/usb/host/ehci-mx6.c              |  205
> >> 
> >> ++++++++++++++++++++++++++++++ 5 files changed, 223 insertions(+), 0
> >> deletions(-)
> >> 
> >>  create mode 100644 drivers/usb/host/ehci-mx6.c
> >> 
> >> diff --git a/arch/arm/cpu/armv7/mx6/clock.c
> >> b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124..ef98563 100644
> >> --- a/arch/arm/cpu/armv7/mx6/clock.c
> >> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> >> @@ -36,6 +36,19 @@ enum pll_clocks {
> >> 
> >>  struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> >> 
> >> +void enable_usboh3_clk(unsigned char enable)
> >> +{
> >> +	u32 reg;
> >> +
> >> +	reg = __raw_readl(&imx_ccm->CCGR6);
> >> +	if (enable)
> >> +		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
> >> +	else
> >> +		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
> >> +	__raw_writel(reg, &imx_ccm->CCGR6);
> >> +
> >> +}
> >> +
> >> 
> >>  static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> >>  {
> >>  
> >>  	u32 div;
> >> 
> >> diff --git a/arch/arm/include/asm/arch-mx6/clock.h
> >> b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644
> >> --- a/arch/arm/include/asm/arch-mx6/clock.h
> >> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> >> @@ -46,5 +46,6 @@ enum mxc_clock {
> >> 
> >>  u32 imx_get_uartclk(void);
> >>  u32 imx_get_fecclk(void);
> >>  unsigned int mxc_get_clock(enum mxc_clock clk);
> >> 
> >> +void enable_usboh3_clk(unsigned char enable);
> >> 
> >>  #endif /* __ASM_ARCH_CLOCK_H */
> >> 
> >> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> >> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3b5fd25..2bfe891 100644
> >> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> >> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> >> @@ -111,6 +111,9 @@
> >> 
> >>  #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
> >>  #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
> >>  #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
> >> 
> >> +#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
> >> +#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
> >> +#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
> >> 
> >>  #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
> >>  #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
> >>  #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
> >> 
> >> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> >> index 77e217f..1b62cc2 100644
> >> --- a/drivers/usb/host/Makefile
> >> +++ b/drivers/usb/host/Makefile
> >> @@ -43,6 +43,7 @@ endif
> >> 
> >>  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
> >>  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
> >>  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
> >> 
> >> +COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
> >> 
> >>  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
> >>  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
> >>  COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
> >> 
> >> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> >> new file mode 100644
> >> index 0000000..b7bf49d
> >> --- /dev/null
> >> +++ b/drivers/usb/host/ehci-mx6.c
> >> @@ -0,0 +1,205 @@
> >> +/*
> >> + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
> >> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> it + * under the terms of the GNU General Public License as published
> >> by the + * Free Software Foundation; either version 2 of the License,
> >> or (at your + * option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful, but
> >> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> >> MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> >> General Public License + * for more details.
> >> + */
> >> +
> >> +#include <common.h>
> >> +#include <usb.h>
> >> +#include <errno.h>
> >> +#include <linux/compiler.h>
> >> +#include <usb/ehci-fsl.h>
> >> +#include <asm/io.h>
> >> +#include <asm/arch/imx-regs.h>
> >> +#include <asm/arch/clock.h>
> >> +#include <asm/arch/mx6x_pins.h>
> >> +#include <asm/arch/iomux-v3.h>
> >> +
> >> +#include "ehci.h"
> >> +#include "ehci-core.h"
> >> +
> >> +#define USB_OTGREGS_OFFSET	0x000
> >> +#define USB_H1REGS_OFFSET	0x200
> >> +#define USB_H2REGS_OFFSET	0x400
> >> +#define USB_H3REGS_OFFSET	0x600
> >> +#define USB_OTHERREGS_OFFSET	0x800
> >> +
> >> +#define USB_H1_CTRL_OFFSET	0x04
> >> +
> >> +#define USBPHY_CTRL				0x00000030
> >> +#define USBPHY_CTRL_SET				0x00000034
> >> +#define USBPHY_CTRL_CLR				0x00000038
> >> +#define USBPHY_CTRL_TOG				0x0000003c
> >> +
> >> +#define USBPHY_PWD				0x00000000
> >> +#define USBPHY_CTRL_SFTRST			0x80000000
> >> +#define USBPHY_CTRL_CLKGATE			0x40000000
> >> +#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
> >> +#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
> 
> These macros are already defined in
> "arch/arm/include/asm/arch-mx28/regs-usbphy.h".
> 
> >> +#define ANADIG_USB2_CHRG_DETECT			0x00000210
> >> +#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
> >> +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
> >> +
> >> +#define ANADIG_USB2_PLL_480_CTRL		0x00000020
> >> +#define ANADIG_USB2_PLL_480_CTRL_SET		0x00000024
> >> +#define ANADIG_USB2_PLL_480_CTRL_CLR		0x00000028
> >> +#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
> >> +#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
> >> +#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
> >> +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
> 
> And these are in "arch/arm/include/asm/arch-mx6/ccm_regs.h", which I
> just realized after a closer look.
> 
> >> +
> >> +#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent 
*/
> >> +#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent
> >> Detection */ +
> >> +/* USBCMD */
> >> +#define UH1_USBCMD_OFFSET	0x140
> >> +#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
> >> +#define UCMD_RESET		(1 << 1) /* controller reset */
> >> +
> >> +static void usbh1_internal_phy_clock_gate(int on)
> >> +{
> >> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> >> +
> >> +	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
> >> +	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
> >> +}
> >> +
> >> +static void usbh1_power_config(void)
> >> +{
> >> +	void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
> >> +
> >> +	/*
> >> +	 * Some phy and power's special controls for host1
> >> +	 * 1. The external charger detector needs to be disabled
> >> +	 * or the signal at DP will be poor
> >> +	 * 2. The PLL's power and output to usb for host 1
> >> +	 * is totally controlled by IC, so the Software only needs
> >> +	 * to enable them at initializtion.
> >> +	 */
> >> +	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
> >> +		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
> >> +		     anatop_base + ANADIG_USB2_CHRG_DETECT);
> >> +
> >> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
> >> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
> >> +
> >> +	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
> >> +		     ANADIG_USB2_PLL_480_CTRL_POWER |
> >> +		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
> >> +		     anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
> > 
> > This part looks mx28ish
> 
> Maybe. While searching I realized that the macros and register addresses
> are already defined in:
> 
> arch/arm/include/asm/arch-mx6/ccm_regs.h
> 
> >> +}
> >> +
> >> +static int usbh1_phy_enable(void)
> >> +{
> >> +	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
> >> +	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
> >> +	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
> >> +						 USB_H1REGS_OFFSET +
> >> +						 UH1_USBCMD_OFFSET);
> >> +	u32 val;
> >> +
> >> +	/* Stop then Reset */
> >> +	val = __raw_readl(usb_cmd);
> >> +	val &= ~UCMD_RUN_STOP;
> >> +	__raw_writel(val, usb_cmd);
> >> +	while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
> >> +		;
> >> +
> >> +	val = __raw_readl(usb_cmd);
> >> +	val |= UCMD_RESET;
> >> +	__raw_writel(val, usb_cmd);
> >> +	while (__raw_readl(usb_cmd) & UCMD_RESET)
> >> +		;
> >> +
> >> +	/* Reset USBPHY module */
> >> +	val = __raw_readl(phy_ctrl);
> >> +	val |= USBPHY_CTRL_SFTRST;
> >> +	__raw_writel(val, phy_ctrl);
> >> +	udelay(10);
> > 
> > This part too.
> > 
> >> +
> >> +	/* Remove CLKGATE and SFTRST */
> >> +	val = __raw_readl(phy_ctrl);
> >> +	val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
> >> +	__raw_writel(val, phy_ctrl);
> >> +	udelay(10);
> > 
> > This too, looks like mx28_reset_block(). But maybe I'm just paranoid and
> > spooky here :)
> > 
> >> +
> >> +	/* Power up the PHY */
> >> +	__raw_writel(0, phy_reg + USBPHY_PWD);
> >> +	/* enable FS/LS device */
> >> +	val = __raw_readl(phy_reg + USBPHY_CTRL);
> >> +	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
> >> +	__raw_writel(val, phy_reg + USBPHY_CTRL);
> > 
> > And maybe not ... this looks like MX28 phy interface.
> 
> I think MX6 and MX28 could share common register definitions. Note sure
> if both will share a lot of code though. To add MX6 USB support to
> ehci-mxs.c seems not straight-forward to me, at least. But I will have a
> closer look next week...

Cool, I believe FSL wanted to demonstrate they can mix alien DNA with human DNA 
(in the words of X-Files ;-) ) ... or to put it simply, they wanted to 
demonstrate they can use the MXS IP in their chips and maybe show the 
acquisition of MXS wasn't a complete waste (this is just a conspiracy theory 
though). They did similar crossbreed with mx53 bootrom.

Marek.

M


Marek.

PS. Good night, damn I'm tired :)

> 
> Wolfgang.
> 
> W
> 
> 
> Wolfgang.

[U-Boot] [PATCH v2 1/2] usb/ehci: Add USB support for the MX6Q

[Stefano Babic]

On 09/02/2012 09:33, Wolfgang Grandegger wrote:
> Currently, only USB Host 1 is supported.
> 
> Cc: Remy Bohmer <linux@bohmer.net>
> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
> ---

Applied to u-boot-imx (after rebasing), thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v2 2/2] mx6qsabrelite: add and enable USB Host 1 support

[Wolfgang Grandegger]

Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   18 ++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 +++++++++++++
 2 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 03a088a..67e46d4 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -140,12 +140,30 @@ static void setup_iomux_enet(void)
 	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 }
 
+iomux_v3_cfg_t usb_pads[] = {
+	MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+	/* Reset USB hub */
+	gpio_direction_output(GPIO_NUMBER(7, 12), 0);
+	mdelay(2);
+	gpio_set_value(GPIO_NUMBER(7, 12), 1);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
        {USDHC3_BASE_ADDR, 1},
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8a95af9..bbd6024 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -78,6 +78,19 @@
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		6
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX              1
-- 
1.7.7.6

[U-Boot] [PATCH v2 2/2] mx6qsabrelite: add and enable USB Host 1 support

[Stefano Babic]

On 09/02/2012 09:33, Wolfgang Grandegger wrote:
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Jason Liu <jason.hui@linaro.org>
> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
> ---

Applied to u-boot-imx (after rebasing), thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v2 0/2] usb/mx6q: USB EHCI support for MX6Q boards

[Dirk Behme]

On 09.02.2012 09:33, Wolfgang Grandegger wrote:
> v1 was bad, sorry. v2 fixes various issues reported by Dirk and Fabio.
> The patches are based on head of Stefano's "u-boot-imx" tree.
> 
> Wolfgang
> 
> Wolfgang Grandegger (2):
>   usb/ehci: Add USB support for the MX6Q
>   mx6qsabrelite: add and enable USB Host 1 support
> 
>  arch/arm/cpu/armv7/mx6/clock.c                |   13 ++
>  arch/arm/include/asm/arch-mx6/clock.h         |    1 +
>  arch/arm/include/asm/arch-mx6/imx-regs.h      |    3 +
>  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   18 +++
>  drivers/usb/host/Makefile                     |    1 +
>  drivers/usb/host/ehci-mx6.c                   |  205 +++++++++++++++++++++++++
>  include/configs/mx6qsabrelite.h               |   13 ++
>  7 files changed, 254 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/usb/host/ehci-mx6.c

Whole series:

Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

Tested-by: Dirk Behme <dirk.behme@de.bosch.com>

on the SabreLite with an USB stick (USB storage) and some fatls commands 
to see if the content of the stick is visible.

Many thanks

Dirk