From: Marek Vasut <marek.vasut@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 0/4 v5] i.MX28: Fix ref_cpu clock setup
Date: Mon, 20 Feb 2012 08:40:16 +0100 [thread overview]
Message-ID: <201202200840.16263.marek.vasut@gmail.com> (raw)
In-Reply-To: <4F41EEC1.9040109@denx.de>
> On 19/02/2012 10:23, Albert ARIBAUD wrote:
> > Hi Robert,
> >
> > Le 15/02/2012 11:29, Robert at domain.unknown a ?crit :
> >> From: Robert Delien<robert@delien.nl>
> >>
> >> This set of patches fixes ref_cpu clock setup.
> >>
> >> Robert Delien (4):
> >> Renamed mx28_register to mx28_register_32 to prepare for
> >>
> >> mx28_register_8
> >>
> >> Introducing 8-bit wide register, mx28_register_8
> >> Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1
> >>
> >> registers
> >>
> >> Preventing needless switching on and off PLL bypass mode, allowing
> >>
> >> allow single-stepping through the SPL
> >
> > P
> > I don't see this V5 on patchwork. Please a V6 with up-to-date Tested-By
> > / Acked-By etc -- and of course make sure the e-mail address stays
> > correct.
>
> > Besides, this touches i.MX, so I think Stefano should be at least Cc:
> Right - Robert, I miss also which is the state of the current patches -
> is there still an issue that avoid boards to boot ?
Yea ... that issue is fixed. I acked patches 1,2,3 ... I'm still unsure about
patch 4.
M
>
> Stefano
next prev parent reply other threads:[~2012-02-20 7:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-15 10:29 [U-Boot] [PATCH 0/4 v5] i.MX28: Fix ref_cpu clock setup Robert at domain.unknown
2012-02-15 10:30 ` [U-Boot] [PATCH 1/4 v5] Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8 Robert at domain.unknown
2012-02-15 12:59 ` Wolfgang Denk
2012-02-15 13:58 ` Robert Deliën
2012-02-15 22:48 ` Wolfgang Denk
2012-02-15 10:30 ` [U-Boot] [PATCH 2/4 v5] Introducing 8-bit wide register, mx28_register_8 Robert at domain.unknown
2012-02-15 10:30 ` [U-Boot] [PATCH 3/4 v5] Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers Robert at domain.unknown
2012-02-15 10:30 ` [U-Boot] [PATCH 4/4 v5] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL Robert at domain.unknown
2012-02-15 10:33 ` [U-Boot] [PATCH 0/4 v5] i.MX28: Fix ref_cpu clock setup Marek Vasut
2012-02-15 10:37 ` Robert Deliën
2012-02-15 11:03 ` Marek Vasut
2012-02-15 13:29 ` Robert Deliën
2012-02-15 22:46 ` Wolfgang Denk
2012-02-15 23:24 ` Fabio Estevam
2012-02-15 12:54 ` Wolfgang Denk
2012-02-15 13:41 ` Robert Deliën
2012-02-19 9:23 ` Albert ARIBAUD
2012-02-20 6:57 ` Stefano Babic
2012-02-20 7:40 ` Marek Vasut [this message]
2012-02-20 7:50 ` Albert ARIBAUD
2012-02-20 12:36 ` Fabio Estevam
2012-02-20 13:14 ` Marek Vasut
[not found] <1329300015-11137-1-git-send-email-robert@delien.nl>
2012-02-15 10:11 ` Marek Vasut
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