From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tom Rini <trini@ti.com>
Date: Mon, 20 Feb 2012 10:36:44 -0700
Subject: [U-Boot] [PATCH 04/17] OMAP5: emif/ddr: Change emif settings as
 required for ES1.0 silicon.
In-Reply-To: <1329480333-18353-5-git-send-email-r.sricharan@ti.com>
References: <1329480333-18353-1-git-send-email-r.sricharan@ti.com>
	<1329480333-18353-5-git-send-email-r.sricharan@ti.com>
Message-ID: <20120220173644.GA20889@bill-the-cat>
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On Fri, Feb 17, 2012 at 05:35:20PM +0530, R Sricharan wrote:

> The OMAP5 silicon has new DDR PHY design, which includes a external PHY
> as well. So configuring the ext PHY parameters here. Also the EMIF timimg
> registers and a couple of DDR mode registers needs to be updated based on
> the testing from the actual silicon.
[snip]
> +		/* external phy 6-24 registers do not change with
> +		 * ddr frequency

Here and elsewhere, incorrectly styled comments.

[snip]
>  /* Maximum delay before Low Power Modes */
> +#ifndef CONFIG_OMAP54XX
>  #define REG_CS_TIM		0xF
> +#else
> +#define REG_CS_TIM              0x0
> +#endif

You used spaces not tabs and I think checkpatch will note that for you
as well (so I expect v2 of the series to be checkpatch clean, aside from
80char wide stuff in those tables).

-- 
Tom