From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 1 Mar 2012 19:34:54 +0100 Subject: [U-Boot] [PATCH 4/7] i.MX28: Enable additional DRAM address bits In-Reply-To: References: <1330294507-6463-1-git-send-email-marex@denx.de> <1330294507-6463-5-git-send-email-marex@denx.de> Message-ID: <201203011934.54714.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > On Sun, Feb 26, 2012 at 7:15 PM, Marek Vasut wrote: > > Signed-off-by: Marek Vasut > > --- > > arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > Could you please elaborate a commit message for this? > > From what I could see this is changing from 0x0f02020a to 0x0f02010a, > and it would be nice to have in the commit message an explanation of > what this register is, what you are changing and why. If I could get my hands on Office 2010 to open that stupid memory thing supplied by freescale, I would. But since I can't ... basically, this is magic which enables all fourteen address lines. From what I remember, the piece at 0xf << 8 says how many address bits are to be disabled and 0 is prohibited. Since all of them should be enabled now, I don't consider it necessary to poke into this anymore. Or does it break anything for you? M