From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/4] net: round up before calling flush_cache
Date: Sun, 1 Apr 2012 15:46:53 +0200 [thread overview]
Message-ID: <201204011546.54069.marex@denx.de> (raw)
In-Reply-To: <1333286581-27939-2-git-send-email-sbabic@denx.de>
Dear Stefano Babic,
> If the range passed to flush_cache is not multiple
> of ARCH_DMA_MINALIGN, a warning due to mislaignment
> is printed.
> Detected with fec_mxc, mx35 boards:
>
> CACHE: Misaligned operation at range [80800000, 8083c310]
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Marek Vasut <marex@denx.de>
> CC: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Wolfgang Denk <wd@denx.de>
> ---
> common/cmd_net.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/common/cmd_net.c b/common/cmd_net.c
> index 65f32bc..a500919 100644
> --- a/common/cmd_net.c
> +++ b/common/cmd_net.c
> @@ -256,7 +256,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t
> *cmdtp, int argc, }
>
> /* flush cache */
> - flush_cache(load_addr, size);
> + flush_cache(load_addr, roundup(size, ARCH_DMA_MINALIGN));
This ain't gonna slide. You might overwrite something, even though this is just
loading into memory, right? I'm not quite sure how to handle this kind of
unaligned access.
But adding at least if (unaligned) debug(...); to aid people easily finding
these trouble would be nice ;-)
> bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
Best regards,
Marek Vasut
next prev parent reply other threads:[~2012-04-01 13:46 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-30 14:02 [U-Boot] [PATCH] ARM1136: add cache flush and invalidate operations Anatolij Gustschin
2012-03-30 14:20 ` Stefano Babic
2012-03-30 14:35 ` Anatolij Gustschin
2012-03-30 15:04 ` Stefano Babic
2012-03-30 15:28 ` Marek Vasut
2012-03-30 15:42 ` Anatolij Gustschin
2012-03-30 15:58 ` Stefano Babic
2012-03-30 16:05 ` Marek Vasut
2012-03-30 16:16 ` Stefano Babic
2012-04-01 13:22 ` [U-Boot] [PATCH 1/4] " Stefano Babic
2012-04-01 13:22 ` [U-Boot] [PATCH 2/4] net: round up before calling flush_cache Stefano Babic
2012-04-01 13:46 ` Marek Vasut [this message]
2012-04-01 14:56 ` Stefano Babic
2012-04-01 15:35 ` Marek Vasut
2012-04-01 19:23 ` Mike Frysinger
2012-04-01 21:00 ` Marek Vasut
2012-04-02 1:38 ` Mike Frysinger
2012-04-02 1:44 ` Marek Vasut
2012-04-02 3:06 ` Mike Frysinger
2012-04-02 3:34 ` Marek Vasut
2012-04-02 5:56 ` Mike Frysinger
2012-04-02 7:13 ` Stefano Babic
2012-04-02 14:03 ` Marek Vasut
2012-04-02 14:38 ` Stefano Babic
2012-04-01 13:23 ` [U-Boot] [PATCH 3/4] mx35: flea3: fix when cache functions are linked Stefano Babic
2012-04-01 13:23 ` [U-Boot] [PATCH 4/4] mx35: mx35pdk: " Stefano Babic
2012-04-02 16:18 ` [U-Boot] [PATCH V3 1/4] ARM1136: add cache flush and invalidate operations Stefano Babic
2012-04-02 16:29 ` Marek Vasut
2012-04-02 16:51 ` Stefano Babic
2012-04-02 16:18 ` [U-Boot] [PATCH V2 2/4] ARM: 926ejs: use debug() for misaligned addresses Stefano Babic
2012-04-02 16:29 ` Marek Vasut
2012-04-02 18:23 ` Mike Frysinger
2012-04-02 18:42 ` Marek Vasut
2012-04-02 19:07 ` Mike Frysinger
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