From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 3 Apr 2012 15:40:08 +0200 Subject: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode In-Reply-To: <1333371476-30691-3-git-send-email-daniel.schwierzeck@googlemail.com> References: <1333371476-30691-1-git-send-email-daniel.schwierzeck@googlemail.com> <1333371476-30691-3-git-send-email-daniel.schwierzeck@googlemail.com> Message-ID: <201204031540.09067.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Mike, there was some issue with this patch? > Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to > use the new config option in dcache_enable(). > > Fix this to avoid inconsistencies if someone wants to disable > and enable D-caches. > > Signed-off-by: Daniel Schwierzeck > --- > arch/mips/cpu/mips32/cache.S | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S > index 5ce0ec4..e683e8b 100644 > --- a/arch/mips/cpu/mips32/cache.S > +++ b/arch/mips/cpu/mips32/cache.S > @@ -30,6 +30,10 @@ > #include > #include > > +#ifndef CONFIG_SYS_MIPS_CACHE_MODE > +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT > +#endif > + > #define RA t8 > > /* > @@ -224,7 +228,7 @@ LEAF(dcache_enable) > mfc0 t0, CP0_CONFIG > ori t0, CONF_CM_CMASK > xori t0, CONF_CM_CMASK > - ori t0, CONF_CM_CACHABLE_NONCOHERENT > + ori t0, CONFIG_SYS_MIPS_CACHE_MODE > mtc0 t0, CP0_CONFIG > jr ra > END(dcache_enable) Best regards, Marek Vasut