[U-Boot] [PATCH 0/3] MIPS: fixes for 2012.04-rc1

[U-Boot] [PATCH 0/3] MIPS: fixes for 2012.04-rc1

[Daniel Schwierzeck]

Hi Marek,

this series collects the bugfix patches from the open patches at patchwork
delegated to you. Only these patches should be merged for the release.
The other patches are superseeded for now.

The series is rebased against v2012.04-rc1 and needs your patch
http://patchwork.ozlabs.org/patch/149924/ to run MAKEALL -a mips.

Daniel Schwierzeck (3):
  MIPS: board.c: fix init of flash data in bd_info
  MIPS: fix inconsistency in config option for cache operation mode
  MIPS: fix endianess handling

 README                         |    6 ++++++
 arch/mips/cpu/mips32/cache.S   |    6 +++++-
 arch/mips/cpu/mips32/config.mk |   21 +++++++++++++++------
 arch/mips/lib/board.c          |    8 ++++++--
 boards.cfg                     |    2 +-
 include/configs/pb1x00.h       |    2 ++
 6 files changed, 35 insertions(+), 10 deletions(-)

--
1.7.9.4

[U-Boot] [PATCH 1/3] MIPS: board.c: fix init of flash data in bd_info

[Daniel Schwierzeck]

Boards with CONFIG_SYS_NO_FLASH should not forced to define
CONFIG_SYS_FLASH_BASE. In this case the flash data in bd_info
should be initialized with 0 like the other archs do.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 arch/mips/lib/board.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index d998f0e..38e6e77 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -294,15 +294,19 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* configure available FLASH banks */
 	size = flash_init();
 	display_flash_config(size);
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
 	bd->bi_flashsize = size;
-#endif
 
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
 #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
 	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for U-Boot */
 #else
 	bd->bi_flashoffset = 0;
 #endif
+#else
+	bd->bi_flashstart = 0;
+	bd->bi_flashsize = 0;
+	bd->bi_flashoffset = 0;
+#endif
 
 #ifdef CONFIG_CMD_NAND
 	puts("NAND:  ");
-- 
1.7.9.4

[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Daniel Schwierzeck]

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 arch/mips/cpu/mips32/cache.S |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 5ce0ec4..e683e8b 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -30,6 +30,10 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 #define RA		t8
 
 /*
@@ -224,7 +228,7 @@ LEAF(dcache_enable)
 	mfc0	t0, CP0_CONFIG
 	ori	t0, CONF_CM_CMASK
 	xori	t0, CONF_CM_CMASK
-	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
 	mtc0	t0, CP0_CONFIG
 	jr	ra
 	END(dcache_enable)
-- 
1.7.9.4

[U-Boot] [PATCH 3/3] MIPS: fix endianess handling

[Daniel Schwierzeck]

Make endianess of target CPU configurable. Use the new config
option for dbau1550_el and pb1000 boards.

Adapt linking of standalone applications to pass through
endianess options to LD.

Build tested with:
 - ELDK 4 mips_4KC- and mips4KCle
 - Sourcery CodeBench Lite 2011.03-93

With this patch all 26 MIPS boards can be compiled now in one step by
running "MAKEALL -a mips".

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 README                         |    6 ++++++
 arch/mips/cpu/mips32/config.mk |   21 +++++++++++++++------
 boards.cfg                     |    2 +-
 include/configs/pb1x00.h       |    2 ++
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/README b/README
index c98afa7..9702067 100644
--- a/README
+++ b/README
@@ -374,6 +374,12 @@ The following options need to be configured:
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 
+- Generic CPU options:
+		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
+
+		Defines the endianess of the CPU. Implementation of those
+		values is arch specific.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk
index 4d1b273..a1cd590 100644
--- a/arch/mips/cpu/mips32/config.mk
+++ b/arch/mips/cpu/mips32/config.mk
@@ -27,14 +27,23 @@
 # Note: Toolchains with binutils prior to v2.16
 # are no longer supported by U-Boot MIPS tree!
 #
-MIPSFLAGS = -march=mips32r2
+MIPSFLAGS := -march=mips32r2
 
+# Handle special prefix in ELDK 4.0 toolchain
 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS = -EL
-else
-ENDIANNESS = -EB
+ENDIANNESS := -EL
 endif
 
-MIPSFLAGS += $(ENDIANNESS)
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ENDIANNESS := -EB
+endif
+
+# Default to EB if no endianess is configured
+ENDIANNESS ?= -EB
 
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS)
+PLATFORM_LDFLAGS += $(ENDIANNESS)
diff --git a/boards.cfg b/boards.cfg
index c6090ba..3cf75c3 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -360,7 +360,7 @@ dbau1000                     mips        mips32      dbau1x00            -
 dbau1100                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1100
 dbau1500                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1500
 dbau1550                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
-dbau1550_el                  mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+dbau1550_el                  mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN
 gth2                         mips        mips32      -                   -              au1x00
 pb1000                       mips        mips32      pb1x00              -              au1x00      pb1x00:PB1000
 incaip                       mips        mips32      incaip              -              incaip
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index eea8ed3..d056884 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -46,6 +46,8 @@
 #endif
 #endif
 
+#define CONFIG_SYS_LITTLE_ENDIAN
+
 #define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
 
 #define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
-- 
1.7.9.4

[U-Boot] [PATCH 0/3] MIPS: fixes for 2012.04-rc1

[Marek Vasut]

Dear Daniel Schwierzeck,

> Hi Marek,
> 
> this series collects the bugfix patches from the open patches at patchwork
> delegated to you. Only these patches should be merged for the release.
> The other patches are superseeded for now.
> 
> The series is rebased against v2012.04-rc1 and needs your patch
> http://patchwork.ozlabs.org/patch/149924/ to run MAKEALL -a mips.

Shinya-san, you ok with these patches hitting .04?

I'll roll then through my -staging if it's fine.

> Daniel Schwierzeck (3):
>   MIPS: board.c: fix init of flash data in bd_info
>   MIPS: fix inconsistency in config option for cache operation mode
>   MIPS: fix endianess handling
> 
>  README                         |    6 ++++++
>  arch/mips/cpu/mips32/cache.S   |    6 +++++-
>  arch/mips/cpu/mips32/config.mk |   21 +++++++++++++++------
>  arch/mips/lib/board.c          |    8 ++++++--
>  boards.cfg                     |    2 +-
>  include/configs/pb1x00.h       |    2 ++
>  6 files changed, 35 insertions(+), 10 deletions(-)
> 
> --
> 1.7.9.4
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Best regards,
Marek Vasut

[U-Boot] [PATCH 0/3] MIPS: fixes for 2012.04-rc1

[Shinya Kuribayashi]

>> this series collects the bugfix patches from the open patches at patchwork
>> delegated to you. Only these patches should be merged for the release.
>> The other patches are superseeded for now.
>>
>> The series is rebased against v2012.04-rc1 and needs your patch
>> http://patchwork.ozlabs.org/patch/149924/ to run MAKEALL -a mips.
>
> Shinya-san, you ok with these patches hitting .04?

Suggestions/comments from Mike to the last submission are not reflected in
[PATCH 2/3] (MIPS: fix inconsistency in config option for cache operation mode),
but other than that these three patches are Ok with me.

> I'll roll then through my -staging if it's fine.

Thanks in advance, I don't have enough bandwidth to catch up with the latest
tree/discussion, nor doing build tests and/or boot tests.

[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Marek Vasut]

Mike, there was some issue with this patch?

> Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
> use the new config option in dcache_enable().
> 
> Fix this to avoid inconsistencies if someone wants to disable
> and enable D-caches.
> 
> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> ---
>  arch/mips/cpu/mips32/cache.S |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
> index 5ce0ec4..e683e8b 100644
> --- a/arch/mips/cpu/mips32/cache.S
> +++ b/arch/mips/cpu/mips32/cache.S
> @@ -30,6 +30,10 @@
>  #include <asm/addrspace.h>
>  #include <asm/cacheops.h>
> 
> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> +#endif
> +
>  #define RA		t8
> 
>  /*
> @@ -224,7 +228,7 @@ LEAF(dcache_enable)
>  	mfc0	t0, CP0_CONFIG
>  	ori	t0, CONF_CM_CMASK
>  	xori	t0, CONF_CM_CMASK
> -	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
> +	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
>  	mtc0	t0, CP0_CONFIG
>  	jr	ra
>  	END(dcache_enable)

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Daniel Schwierzeck]

Hi,

On Tue, Apr 3, 2012 at 3:40 PM, Marek Vasut <marex@denx.de> wrote:
> Mike, there was some issue with this patch?
>
>> Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
>> use the new config option in dcache_enable().

this commit refers to a patch that I sent a while ago as preparation
for supporting Lantiq SoCs.
Some Lantiq SoCs wants CONF_CM_CACHABLE_NO_WA  instead of the
hard-coded CONF_CM_CACHABLE_NONCOHERENT.
So I created a config option for the required cache mode.

>>
>> Fix this to avoid inconsistencies if someone wants to disable
>> and enable D-caches.
>>
>> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
>> ---
>> ?arch/mips/cpu/mips32/cache.S | ? ?6 +++++-
>> ?1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
>> index 5ce0ec4..e683e8b 100644
>> --- a/arch/mips/cpu/mips32/cache.S
>> +++ b/arch/mips/cpu/mips32/cache.S
>> @@ -30,6 +30,10 @@
>> ?#include <asm/addrspace.h>
>> ?#include <asm/cacheops.h>
>>
>> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
>> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
>> +#endif
>> +
>> ?#define RA ? ? ? ? ? t8
>>
>> ?/*
>> @@ -224,7 +228,7 @@ LEAF(dcache_enable)
>> ? ? ? mfc0 ? ?t0, CP0_CONFIG
>> ? ? ? ori ? ? t0, CONF_CM_CMASK
>> ? ? ? xori ? ?t0, CONF_CM_CMASK
>> - ? ? ori ? ? t0, CONF_CM_CACHABLE_NONCOHERENT
>> + ? ? ori ? ? t0, CONFIG_SYS_MIPS_CACHE_MODE
>> ? ? ? mtc0 ? ?t0, CP0_CONFIG
>> ? ? ? jr ? ? ?ra
>> ? ? ? END(dcache_enable)
>
> Best regards,
> Marek Vasut

I only changed start.S and forgot to change this code part too. That is why I
created this patch to fix this inconsistency.

-- 
Best regards,
Daniel

[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Marek Vasut]

Dear Daniel Schwierzeck,

> Hi,
> 
> On Tue, Apr 3, 2012 at 3:40 PM, Marek Vasut <marex@denx.de> wrote:
> > Mike, there was some issue with this patch?
> > 
> >> Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
> >> use the new config option in dcache_enable().
> 
> this commit refers to a patch that I sent a while ago as preparation
> for supporting Lantiq SoCs.
> Some Lantiq SoCs wants CONF_CM_CACHABLE_NO_WA  instead of the
> hard-coded CONF_CM_CACHABLE_NONCOHERENT.
> So I created a config option for the required cache mode.
> 
> >> Fix this to avoid inconsistencies if someone wants to disable
> >> and enable D-caches.
> >> 
> >> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> >> ---
> >>  arch/mips/cpu/mips32/cache.S |    6 +++++-
> >>  1 file changed, 5 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
> >> index 5ce0ec4..e683e8b 100644
> >> --- a/arch/mips/cpu/mips32/cache.S
> >> +++ b/arch/mips/cpu/mips32/cache.S
> >> @@ -30,6 +30,10 @@
> >>  #include <asm/addrspace.h>
> >>  #include <asm/cacheops.h>
> >> 
> >> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
> >> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> >> +#endif
> >> +
> >>  #define RA           t8
> >> 
> >>  /*
> >> @@ -224,7 +228,7 @@ LEAF(dcache_enable)
> >>       mfc0    t0, CP0_CONFIG
> >>       ori     t0, CONF_CM_CMASK
> >>       xori    t0, CONF_CM_CMASK
> >> -     ori     t0, CONF_CM_CACHABLE_NONCOHERENT
> >> +     ori     t0, CONFIG_SYS_MIPS_CACHE_MODE
> >>       mtc0    t0, CP0_CONFIG
> >>       jr      ra
> >>       END(dcache_enable)
> > 
> > Best regards,
> > Marek Vasut
> 
> I only changed start.S and forgot to change this code part too. That is why
> I created this patch to fix this inconsistency.

I see ... so this fixes some other commit. What was Shinya-san's concern, that 
you only changed this file?

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/3] MIPS: fix endianess handling

[Mike Frysinger]

On Monday 02 April 2012 08:57:56 Daniel Schwierzeck wrote:
> Make endianess of target CPU configurable. Use the new config
> option for dbau1550_el and pb1000 boards.
> 
> Adapt linking of standalone applications to pass through
> endianess options to LD.

Acked-by: Mike Frysinger <vapier@gentoo.org>

note: we could unify the -EL/-EB handling in the top level as those options 
are the same for linkers.  it's only the CFLAGS that differ :(.
-mike
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[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Mike Frysinger]

On Tuesday 03 April 2012 09:40:08 Marek Vasut wrote:
> Mike, there was some issue with this patch?

i had feedback on the endian flags last time Daniel posted it, but i don't 
think i ever gave feedback on this ... i certainly don't know mips asm beyond 
the extreme basics ;).

was there a patchwork URL or mailing list archive for me to check ?
-mike
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[U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode

[Shinya Kuribayashi]

On Wed, Apr 4, 2012 at 1:09 AM, Marek Vasut <marex@denx.de> wrote:
>> I only changed start.S and forgot to change this code part too. That is why
>> I created this patch to fix this inconsistency.
>
> I see ... so this fixes some other commit. What was Shinya-san's concern, that
> you only changed this file?

On Wed, Apr 4, 2012 at 5:33 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Tuesday 03 April 2012 09:40:08 Marek Vasut wrote:
>> Mike, there was some issue with this patch?
>
> i had feedback on the endian flags last time Daniel posted it, but i don't
> think i ever gave feedback on this ... i certainly don't know mips asm beyond
> the extreme basics ;).

Apologies for confusing, I intended to refer to PATCH 3/3, not 2/3.
If everybody is Ok with 3/3 as-is, I'm fine.

  Shinya

[U-Boot] [PATCH 3/3] MIPS: fix endianess handling

[Marek Vasut]

Dear Mike Frysinger,

> On Monday 02 April 2012 08:57:56 Daniel Schwierzeck wrote:
> > Make endianess of target CPU configurable. Use the new config
> > option for dbau1550_el and pb1000 boards.
> > 
> > Adapt linking of standalone applications to pass through
> > endianess options to LD.
> 
> Acked-by: Mike Frysinger <vapier@gentoo.org>
> 
> note: we could unify the -EL/-EB handling in the top level as those options
> are the same for linkers.  it's only the CFLAGS that differ :(.

Agreed ... so I'll be pushing those for .04 release as fixes?

> -mike

Best regards,
Marek Vasut