* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
@ 2012-05-02 13:52 ` Rajeshwari Shinde
2012-05-02 15:53 ` Marek Vasut
2012-05-03 7:14 ` Minkyu Kang
2012-05-02 13:52 ` [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register Rajeshwari Shinde
` (4 subsequent siblings)
5 siblings, 2 replies; 21+ messages in thread
From: Rajeshwari Shinde @ 2012-05-02 13:52 UTC (permalink / raw)
To: u-boot
This patch add structure for SYSREG.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
arch/arm/include/asm/arch-exynos/sysreg.h | 43 +++++++++++++++++++++++++++++
1 files changed, 43 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
new file mode 100644
index 0000000..aca4b2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/sysreg.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for sysreg
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_SYSREG_H__
+#define __EXYNOS5_SYSREG_H__
+
+#ifndef __ASSEMBLY__
+/* sysreg map */
+struct exynos5_sysreg {
+ /* Add registers as and when required */
+ unsigned char res1[0x214];
+ unsigned int disp1blk_cfg;
+ unsigned int dispblk_cfg2;
+ unsigned int hdcp_e_fuse_mem_cfg;
+ unsigned int gsclblk_cfg0;
+ unsigned int gsclblk_cfg1;
+ unsigned int ispblk_cfg;
+ unsigned int usb20_phy_cfg;
+ unsigned char res2[0x29c];
+ unsigned int mipi_dphy;
+ unsigned int dptx_phy;
+ unsigned int phyclk_sel;
+};
+#endif
+
+#endif
--
1.7.4.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-02 13:52 ` [U-Boot] [PATCH 1/5] exynos5: Add system register structure Rajeshwari Shinde
@ 2012-05-02 15:53 ` Marek Vasut
2012-05-03 1:47 ` Kyungmin Park
2012-05-03 5:38 ` Chander Kashyap
2012-05-03 7:14 ` Minkyu Kang
1 sibling, 2 replies; 21+ messages in thread
From: Marek Vasut @ 2012-05-02 15:53 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari Shinde,
> This patch add structure for SYSREG.
Ccing Minkyu. Can I get your opinion on these patches please?
>
> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/include/asm/arch-exynos/sysreg.h | 43
> +++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0
> deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>
> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h
> b/arch/arm/include/asm/arch-exynos/sysreg.h new file mode 100644
> index 0000000..aca4b2b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
> @@ -0,0 +1,43 @@
> +/*
> + * (C) Copyright 2012 Samsung Electronics
> + * Register map for sysreg
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __EXYNOS5_SYSREG_H__
> +#define __EXYNOS5_SYSREG_H__
> +
> +#ifndef __ASSEMBLY__
> +/* sysreg map */
> +struct exynos5_sysreg {
> + /* Add registers as and when required */
> + unsigned char res1[0x214];
> + unsigned int disp1blk_cfg;
> + unsigned int dispblk_cfg2;
> + unsigned int hdcp_e_fuse_mem_cfg;
> + unsigned int gsclblk_cfg0;
> + unsigned int gsclblk_cfg1;
> + unsigned int ispblk_cfg;
> + unsigned int usb20_phy_cfg;
> + unsigned char res2[0x29c];
> + unsigned int mipi_dphy;
> + unsigned int dptx_phy;
> + unsigned int phyclk_sel;
> +};
> +#endif
> +
> +#endif
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-02 15:53 ` Marek Vasut
@ 2012-05-03 1:47 ` Kyungmin Park
2012-05-03 5:38 ` Chander Kashyap
1 sibling, 0 replies; 21+ messages in thread
From: Kyungmin Park @ 2012-05-03 1:47 UTC (permalink / raw)
To: u-boot
+ Minkyu,
On 5/3/12, Marek Vasut <marex@denx.de> wrote:
> Dear Rajeshwari Shinde,
>
>> This patch add structure for SYSREG.
>
> Ccing Minkyu. Can I get your opinion on these patches please?
>
>>
>> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>> arch/arm/include/asm/arch-exynos/sysreg.h | 43
>> +++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0
>> deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h
>> b/arch/arm/include/asm/arch-exynos/sysreg.h new file mode 100644
>> index 0000000..aca4b2b
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
>> @@ -0,0 +1,43 @@
>> +/*
>> + * (C) Copyright 2012 Samsung Electronics
>> + * Register map for sysreg
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef __EXYNOS5_SYSREG_H__
>> +#define __EXYNOS5_SYSREG_H__
>> +
>> +#ifndef __ASSEMBLY__
>> +/* sysreg map */
>> +struct exynos5_sysreg {
>> + /* Add registers as and when required */
>> + unsigned char res1[0x214];
>> + unsigned int disp1blk_cfg;
>> + unsigned int dispblk_cfg2;
>> + unsigned int hdcp_e_fuse_mem_cfg;
>> + unsigned int gsclblk_cfg0;
>> + unsigned int gsclblk_cfg1;
>> + unsigned int ispblk_cfg;
>> + unsigned int usb20_phy_cfg;
>> + unsigned char res2[0x29c];
>> + unsigned int mipi_dphy;
>> + unsigned int dptx_phy;
>> + unsigned int phyclk_sel;
>> +};
>> +#endif
>> +
>> +#endif
>
> Best regards,
> Marek Vasut
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-02 15:53 ` Marek Vasut
2012-05-03 1:47 ` Kyungmin Park
@ 2012-05-03 5:38 ` Chander Kashyap
1 sibling, 0 replies; 21+ messages in thread
From: Chander Kashyap @ 2012-05-03 5:38 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari,
On 2 May 2012 21:23, Marek Vasut <marex@denx.de> wrote:
> Dear Rajeshwari Shinde,
>
>> This patch add structure for SYSREG.
>
> Ccing Minkyu. Can I get your opinion on these patches please?
>
>>
>> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>> ?arch/arm/include/asm/arch-exynos/sysreg.h | ? 43
>> +++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0
>> deletions(-)
>> ?create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h
>> b/arch/arm/include/asm/arch-exynos/sysreg.h new file mode 100644
>> index 0000000..aca4b2b
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
>> @@ -0,0 +1,43 @@
>> +/*
>> + * (C) Copyright 2012 Samsung Electronics
>> + * Register map for sysreg
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef __EXYNOS5_SYSREG_H__
>> +#define __EXYNOS5_SYSREG_H__
>> +
>> +#ifndef __ASSEMBLY__
>> +/* sysreg map */
>> +struct exynos5_sysreg {
>> + ? ? /* Add registers as and when required */
>> + ? ? unsigned char ? res1[0x214];
>> + ? ? unsigned int ? ?disp1blk_cfg;
>> + ? ? unsigned int ? ?dispblk_cfg2;
>> + ? ? unsigned int ? ?hdcp_e_fuse_mem_cfg;
>> + ? ? unsigned int ? ?gsclblk_cfg0;
>> + ? ? unsigned int ? ?gsclblk_cfg1;
>> + ? ? unsigned int ? ?ispblk_cfg;
>> + ? ? unsigned int ? ?usb20_phy_cfg;
>> + ? ? unsigned char ? res2[0x29c];
>> + ? ? unsigned int ? ?mipi_dphy;
>> + ? ? unsigned int ? ?dptx_phy;
>> + ? ? unsigned int ? ?phyclk_sel;
>> +};
>> +#endif
>> +
>> +#endif
>
> Best regards,
> Marek Vasut
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Acked-by: Chander kashyap <chander.kashyap@linaro.org>
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-02 13:52 ` [U-Boot] [PATCH 1/5] exynos5: Add system register structure Rajeshwari Shinde
2012-05-02 15:53 ` Marek Vasut
@ 2012-05-03 7:14 ` Minkyu Kang
2012-05-03 12:21 ` Rajeshwari Birje
1 sibling, 1 reply; 21+ messages in thread
From: Minkyu Kang @ 2012-05-03 7:14 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari Shinde,
On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> This patch add structure for SYSREG.
>
> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> ?arch/arm/include/asm/arch-exynos/sysreg.h | ? 43 +++++++++++++++++++++++++++++
> ?1 files changed, 43 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>
> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
> new file mode 100644
> index 0000000..aca4b2b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
> @@ -0,0 +1,43 @@
> +/*
> + * (C) Copyright 2012 Samsung Electronics
> + * Register map for sysreg
Please add your name.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __EXYNOS5_SYSREG_H__
please modify it to __ASM_ARM_ARCH_SYSREG_H__.
> +#define __EXYNOS5_SYSREG_H__
> +
> +#ifndef __ASSEMBLY__
> +/* sysreg map */
> +struct exynos5_sysreg {
> + ? ? ? /* Add registers as and when required */
> + ? ? ? unsigned char ? res1[0x214];
> + ? ? ? unsigned int ? ?disp1blk_cfg;
> + ? ? ? unsigned int ? ?dispblk_cfg2;
> + ? ? ? unsigned int ? ?hdcp_e_fuse_mem_cfg;
> + ? ? ? unsigned int ? ?gsclblk_cfg0;
> + ? ? ? unsigned int ? ?gsclblk_cfg1;
> + ? ? ? unsigned int ? ?ispblk_cfg;
> + ? ? ? unsigned int ? ?usb20_phy_cfg;
> + ? ? ? unsigned char ? res2[0x29c];
> + ? ? ? unsigned int ? ?mipi_dphy;
> + ? ? ? unsigned int ? ?dptx_phy;
> + ? ? ? unsigned int ? ?phyclk_sel;
> +};
> +#endif
> +
> +#endif
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 1/5] exynos5: Add system register structure
2012-05-03 7:14 ` Minkyu Kang
@ 2012-05-03 12:21 ` Rajeshwari Birje
0 siblings, 0 replies; 21+ messages in thread
From: Rajeshwari Birje @ 2012-05-03 12:21 UTC (permalink / raw)
To: u-boot
Hi Minkyu,
Thank you for the comments.
On Thu, May 3, 2012 at 12:44 PM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari Shinde,
>
> On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
>> This patch add structure for SYSREG.
>>
>> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>> ?arch/arm/include/asm/arch-exynos/sysreg.h | ? 43 +++++++++++++++++++++++++++++
>> ?1 files changed, 43 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
>> new file mode 100644
>> index 0000000..aca4b2b
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
>> @@ -0,0 +1,43 @@
>> +/*
>> + * (C) Copyright 2012 Samsung Electronics
>> + * Register map for sysreg
>
> Please add your name.
-- will do so.
>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef __EXYNOS5_SYSREG_H__
>
> please modify it to __ASM_ARM_ARCH_SYSREG_H__.
-- Will correct this
>
>> +#define __EXYNOS5_SYSREG_H__
>> +
>> +#ifndef __ASSEMBLY__
>> +/* sysreg map */
>> +struct exynos5_sysreg {
>> + ? ? ? /* Add registers as and when required */
>> + ? ? ? unsigned char ? res1[0x214];
>> + ? ? ? unsigned int ? ?disp1blk_cfg;
>> + ? ? ? unsigned int ? ?dispblk_cfg2;
>> + ? ? ? unsigned int ? ?hdcp_e_fuse_mem_cfg;
>> + ? ? ? unsigned int ? ?gsclblk_cfg0;
>> + ? ? ? unsigned int ? ?gsclblk_cfg1;
>> + ? ? ? unsigned int ? ?ispblk_cfg;
>> + ? ? ? unsigned int ? ?usb20_phy_cfg;
>> + ? ? ? unsigned char ? res2[0x29c];
>> + ? ? ? unsigned int ? ?mipi_dphy;
>> + ? ? ? unsigned int ? ?dptx_phy;
>> + ? ? ? unsigned int ? ?phyclk_sel;
>> +};
>> +#endif
>> +
>> +#endif
>
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Regards,
Rajeshwari Shinde.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
2012-05-02 13:52 ` [U-Boot] [PATCH 1/5] exynos5: Add system register structure Rajeshwari Shinde
@ 2012-05-02 13:52 ` Rajeshwari Shinde
2012-05-03 6:13 ` Chander Kashyap
2012-05-02 13:52 ` [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI Rajeshwari Shinde
` (3 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Rajeshwari Shinde @ 2012-05-02 13:52 UTC (permalink / raw)
To: u-boot
This patch adds power mananagement register structure for exynos5 SoC.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/include/asm/arch-exynos/power.h | 622 ++++++++++++++++++++++++++++++
1 files changed, 622 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 6444fd0..4236beb 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -225,6 +225,628 @@ struct exynos4_power {
unsigned int gps_alive_status;
unsigned int gps_alive_option;
};
+
+struct exynos5_power {
+ unsigned int om_stat;
+ unsigned char res1[0x18];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned char res2[0x1dc];
+ unsigned int central_seq_configuration;
+ unsigned int central_seq_status;
+ unsigned int central_seq_option;
+ unsigned char res3[0x14];
+ unsigned int seq_transition0;
+ unsigned int seq_transition1;
+ unsigned int seq_transition2;
+ unsigned int seq_transition3;
+ unsigned int seq_transition4;
+ unsigned int seq_transition5;
+ unsigned int seq_transition6;
+ unsigned int seq_transition7;
+ unsigned int central_seq_dmc_configuration;
+ unsigned int central_seq_dmc_status;
+ unsigned int central_seq_dmc_option;
+ unsigned char res4[0x14];
+ unsigned int seq_dmc_transition0;
+ unsigned int seq_dmc_transition1;
+ unsigned int seq_dmc_transition2;
+ unsigned int seq_dmc_transition3;
+ unsigned int seq_dmc_transition4;
+ unsigned int seq_dmc_transition5;
+ unsigned int seq_dmc_transition6;
+ unsigned int seq_dmc_transition7;
+ unsigned char res5[0x180];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int automatic_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned int mask_wreset_request;
+ unsigned char res6[0xec];
+ unsigned int reset_sequencer_configuration;
+ unsigned int reset_sequencer_status;
+ unsigned int reset_sequencer_option;
+ unsigned char res7[0xf4];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned int wakeup_interrupt;
+ unsigned char res8[0x10];
+ unsigned int wakeup_stat_dmc;
+ unsigned int eint_wakeup_mask_dmc;
+ unsigned int wakeup_mask_dmc;
+ unsigned int wakeup_interrupt_dmc;
+ unsigned char res9[0xd0];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdrd_phy_control;
+ unsigned int usbhost_phy_control;
+ unsigned int efnand_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned int mtcadc_phy_control;
+ unsigned int dptx_phy_control;
+ unsigned int sata_phy_control;
+ unsigned char res10[0xd8];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int sysip_dat0;
+ unsigned int sysip_dat1;
+ unsigned int sysip_dat2;
+ unsigned int sysip_dat3;
+ unsigned char res11[0xe0];
+ unsigned int pmu_spare0;
+ unsigned int pmu_spare1;
+ unsigned int pmu_spare2;
+ unsigned int pmu_spare3;
+ unsigned char res12[0x70];
+ unsigned int irom_data_reg0;
+ unsigned int irom_data_reg1;
+ unsigned int irom_data_reg2;
+ unsigned int irom_data_reg3;
+ unsigned char res13[0x70];
+ unsigned int pmu_debug;
+ unsigned char res14[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_central_sys_pwr_reg;
+ unsigned char res15[0x4];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_central_sys_pwr_reg;
+ unsigned char res16[0x24];
+ unsigned int fsys_arm_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_central_sys_pwr_reg;
+ unsigned char res17[0x4];
+ unsigned int isp_arm_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_central_sys_pwr_reg;
+ unsigned char res18[0x24];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res19[0x3c];
+ unsigned int arm_l2_sys_pwr_reg;
+ unsigned char res20[0x3c];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res21[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res22[0x10];
+ unsigned int cmu_aclkstop_dmc_sys_pwr_reg;
+ unsigned int cmu_sclkstop_dmc_sys_pwr_reg;
+ unsigned char res23[0x4];
+ unsigned int cmu_reset_dmc_sys_pwr_reg;
+ unsigned char res24[0x8];
+ unsigned int ddrphy_dlllock_sys_pwr_reg;
+ unsigned char res25[0x4];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned int bpll_sysclk_sys_pwr_reg;
+ unsigned int cpll_sysclk_sys_pwr_reg;
+ unsigned int gpll_sysclk_sys_pwr_reg;
+ unsigned char res26[0x8];
+ unsigned int mplluser_sysclk_sys_pwr_reg;
+ unsigned char res27[0x8];
+ unsigned int bplluser_sysclk_sys_pwr_reg;
+ unsigned char res28[0xc];
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res29[0x4];
+ unsigned int top_bus_dmc_sys_pwr_reg;
+ unsigned int top_retention_dmc_sys_pwr_reg;
+ unsigned int top_pwr_dmc_sys_pwr_reg;
+ unsigned char res30[0x4];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned int oscclk_gate_sys_pwr_reg;
+ unsigned char res31[0x8];
+ unsigned int logic_reset_dmc_sys_pwr_reg;
+ unsigned int oscclk_gate_dmc_sys_pwr_reg;
+ unsigned char res32[0x8];
+ unsigned int usbotg_mem_sys_pwr_reg;
+ unsigned char res33[0x4];
+ unsigned int g2d_mem_sys_pwr_reg;
+ unsigned int usbdrd_mem_sys_pwr_reg;
+ unsigned int efnand_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned int rotator_mem_sys_pwr_reg;
+ unsigned int intram_mem_sys_pwr_reg;
+ unsigned int introm_mem_sys_pwr_reg;
+ unsigned int jpeg_mem_sys_pwr_reg;
+ unsigned int hsi_mem_sys_pwr_reg;
+ unsigned char res34[0x4];
+ unsigned int mcuiop_mem_sys_pwr_reg;
+ unsigned char res35[0x4];
+ unsigned int sata_mem_sys_pwr_reg;
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_mau_sys_pwr_reg;
+ unsigned int pad_retention_jtag_sys_pwr_reg;
+ unsigned char res36[0xc];
+ unsigned int pad_retention_mmc2_sys_pwr_reg;
+ unsigned int pad_retention_mmc3_sys_pwr_reg;
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmc0_sys_pwr_reg;
+ unsigned int pad_retention_mmc1_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned int pad_retention_spi_sys_pwr_reg;
+ unsigned int pad_retention_gpio_dmc_sys_pwr_reg;
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res37[0xc];
+ unsigned int pad_isolation_dmc_sys_pwr_reg;
+ unsigned char res38[0xc];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res39[0x20];
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res40[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res41[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res42[0x1c];
+ unsigned int gpio_mode_dmc_sys_pwr_reg;
+ unsigned char res43[0x1c];
+ unsigned int gpio_mode_mau_sys_pwr_reg;
+ unsigned int top_asb_reset_sys_pwr_reg;
+ unsigned int top_asb_isolation_sys_pwr_reg;
+ unsigned char res44[0xb4];
+ unsigned int gscl_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned char res45[0x4];
+ unsigned int disp1_sys_pwr_reg;
+ unsigned int mau_sys_pwr_reg;
+ unsigned char res46[0x64];
+ unsigned int cmu_clkstop_gscl_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned char res47[0x4];
+ unsigned int cmu_clkstop_disp1_sys_pwr_reg;
+ unsigned int cmu_clkstop_mau_sys_pwr_reg;
+ unsigned char res48[0x24];
+ unsigned int cmu_sysclk_gscl_sys_pwr_reg;
+ unsigned int cmu_sysclk_isp_sys_pwr_reg;
+ unsigned int cmu_sysclk_mfc_sys_pwr_reg;
+ unsigned int cmu_sysclk_g3d_sys_pwr_reg;
+ unsigned char res49[0x4];
+ unsigned int cmu_sysclk_disp1_sys_pwr_reg;
+ unsigned int cmu_sysclk_mau_sys_pwr_reg;
+ unsigned char res50[0xa4];
+ unsigned int cmu_reset_gscl_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned char res51[0x4];
+ unsigned int cmu_reset_disp1_sys_pwr_reg;
+ unsigned int cmu_reset_mau_sys_pwr_reg;
+ unsigned char res52[0xa64];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res53[0x14];
+ unsigned int dis_irq_arm_core0_local_configuration;
+ unsigned int dis_irq_arm_core0_local_status;
+ unsigned int dis_irq_arm_core0_local_option;
+ unsigned char res54[0x14];
+ unsigned int dis_irq_arm_core0_central_configuration;
+ unsigned int dis_irq_arm_core0_central_status;
+ unsigned int dis_irq_arm_core0_central_option;
+ unsigned char res55[0x34];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res56[0x14];
+ unsigned int dis_irq_arm_core1_local_configuration;
+ unsigned int dis_irq_arm_core1_local_status;
+ unsigned int dis_irq_arm_core1_local_option;
+ unsigned char res57[0x14];
+ unsigned int dis_irq_arm_core1_central_configuration;
+ unsigned int dis_irq_arm_core1_central_status;
+ unsigned int dis_irq_arm_core1_central_option;
+ unsigned char res58[0x134];
+ unsigned int fsys_arm_configuration;
+ unsigned int fsys_arm_status;
+ unsigned int fsys_arm_option;
+ unsigned char res59[0x14];
+ unsigned int dis_irq_fsys_arm_local_configuration;
+ unsigned int dis_irq_fsys_arm_local_status;
+ unsigned int dis_irq_fsys_arm_local_option;
+ unsigned char res60[0x14];
+ unsigned int dis_irq_fsys_arm_central_configuration;
+ unsigned int dis_irq_fsys_arm_central_status;
+ unsigned int dis_irq_fsys_arm_central_option;
+ unsigned char res61[0x34];
+ unsigned int isp_arm_configuration;
+ unsigned int isp_arm_status;
+ unsigned int isp_arm_option;
+ unsigned char res62[0x14];
+ unsigned int dis_irq_isp_arm_local_configuration;
+ unsigned int dis_irq_isp_arm_local_status;
+ unsigned int dis_irq_isp_arm_local_option;
+ unsigned char res63[0x14];
+ unsigned int dis_irq_isp_arm_central_configuration;
+ unsigned int dis_irq_isp_arm_central_status;
+ unsigned int dis_irq_isp_arm_central_option;
+ unsigned char res64[0x134];
+ unsigned int arm_common_configuration;
+ unsigned int arm_common_status;
+ unsigned int arm_common_option;
+ unsigned char res65[0x1f4];
+ unsigned int arm_l2_configuration;
+ unsigned int arm_l2_status;
+ unsigned int arm_l2_option;
+ unsigned char res66[0x1f4];
+ unsigned int cmu_aclkstop_configuration;
+ unsigned int cmu_aclkstop_status;
+ unsigned int cmu_aclkstop_option;
+ unsigned char res67[0x14];
+ unsigned int cmu_sclkstop_configuration;
+ unsigned int cmu_sclkstop_status;
+ unsigned int cmu_sclkstop_option;
+ unsigned char res68[0x34];
+ unsigned int cmu_reset_configuration;
+ unsigned int cmu_reset_status;
+ unsigned int cmu_reset_option;
+ unsigned char res69[0x94];
+ unsigned int cmu_aclkstop_dmc_configuration;
+ unsigned int cmu_aclkstop_dmc_status;
+ unsigned int cmu_aclkstop_dmc_option;
+ unsigned char res70[0x14];
+ unsigned int cmu_sclkstop_dmc_configuration;
+ unsigned int cmu_sclkstop_dmc_status;
+ unsigned int cmu_sclkstop_dmc_option;
+ unsigned char res71[0x34];
+ unsigned int cmu_reset_dmc_configuration;
+ unsigned int cmu_reset_dmc_status;
+ unsigned int cmu_reset_dmc_option;
+ unsigned char res72[0x54];
+ unsigned int ddrphy_dlllock_configuration;
+ unsigned int ddrphy_dlllock_status;
+ unsigned int ddrphy_dlllock_option;
+ unsigned char res73[0x34];
+ unsigned int apll_sysclk_configuration;
+ unsigned int apll_sysclk_status;
+ unsigned int apll_sysclk_option;
+ unsigned char res74[0x18];
+ unsigned int mpll_sysclk_status;
+ unsigned int mpll_sysclk_option;
+ unsigned char res75[0x14];
+ unsigned int vpll_sysclk_configuration;
+ unsigned int vpll_sysclk_status;
+ unsigned int vpll_sysclk_option;
+ unsigned char res76[0x14];
+ unsigned int epll_sysclk_configuration;
+ unsigned int epll_sysclk_status;
+ unsigned int epll_sysclk_option;
+ unsigned char res77[0x14];
+ unsigned int bpll_sysclk_configuration;
+ unsigned int bpll_sysclk_status;
+ unsigned int bpll_sysclk_option;
+ unsigned char res78[0x14];
+ unsigned int cpll_sysclk_configuration;
+ unsigned int cpll_sysclk_status;
+ unsigned int cpll_sysclk_option;
+ unsigned char res79[0x14];
+ unsigned int gpll_sysclk_configuration;
+ unsigned int gpll_sysclk_status;
+ unsigned int gpll_sysclk_option;
+ unsigned char res80[0x54];
+ unsigned int mplluser_sysclk_configuration;
+ unsigned int mplluser_sysclk_status;
+ unsigned int mplluser_sysclk_option;
+ unsigned char res81[0x54];
+ unsigned int bplluser_sysclk_configuration;
+ unsigned int bplluser_sysclk_status;
+ unsigned int bplluser_sysclk_option;
+ unsigned char res82[0x74];
+ unsigned int top_bus_configuration;
+ unsigned int top_bus_status;
+ unsigned int top_bus_option;
+ unsigned char res83[0x14];
+ unsigned int top_retention_configuration;
+ unsigned int top_retention_status;
+ unsigned int top_retention_option;
+ unsigned char res84[0x14];
+ unsigned int top_pwr_configuration;
+ unsigned int top_pwr_status;
+ unsigned int top_pwr_option;
+ unsigned char res85[0x34];
+ unsigned int top_bus_dmc_configuration;
+ unsigned int top_bus_dmc_status;
+ unsigned int top_bus_dmc_option;
+ unsigned char res86[0x14];
+ unsigned int top_retention_dmc_configuration;
+ unsigned int top_retention_dmc_status;
+ unsigned int top_retention_dmc_option;
+ unsigned char res87[0x14];
+ unsigned int top_pwr_dmc_configuration;
+ unsigned int top_pwr_dmc_status;
+ unsigned int top_pwr_dmc_option;
+ unsigned char res88[0x34];
+ unsigned int logic_reset_configuration;
+ unsigned int logic_reset_status;
+ unsigned int logic_reset_option;
+ unsigned char res89[0x14];
+ unsigned int oscclk_gate_configuration;
+ unsigned int oscclk_gate_status;
+ unsigned int oscclk_gate_option;
+ unsigned char res90[0x54];
+ unsigned int logic_reset_dmc_configuration;
+ unsigned int logic_reset_dmc_status;
+ unsigned int logic_reset_dmc_option;
+ unsigned char res91[0x14];
+ unsigned int oscclk_gate_dmc_configuration;
+ unsigned int oscclk_gate_dmc_status;
+ unsigned int oscclk_gate_dmc_option;
+ unsigned char res92[0x54];
+ unsigned int usbotg_mem_configuration;
+ unsigned int usbotg_mem_status;
+ unsigned int usbotg_mem_option;
+ unsigned char res93[0x34];
+ unsigned int g2d_mem_configuration;
+ unsigned int g2d_mem_status;
+ unsigned int g2d_mem_option;
+ unsigned char res94[0x14];
+ unsigned int usbdrd_mem_configuration;
+ unsigned int usbdrd_mem_status;
+ unsigned int usbdrd_mem_option;
+ unsigned char res95[0x14];
+ unsigned int efnand_mem_configuration;
+ unsigned int efnand_mem_status;
+ unsigned int efnand_mem_option;
+ unsigned char res96[0x14];
+ unsigned int cssys_mem_configuration;
+ unsigned int cssys_mem_status;
+ unsigned int cssys_mem_option;
+ unsigned char res97[0x14];
+ unsigned int secss_mem_configuration;
+ unsigned int secss_mem_status;
+ unsigned int secss_mem_option;
+ unsigned char res98[0x14];
+ unsigned int rotator_mem_configuration;
+ unsigned int rotator_mem_status;
+ unsigned int rotator_mem_option;
+ unsigned char res99[0x14];
+ unsigned int intram_mem_configuration;
+ unsigned int intram_mem_status;
+ unsigned int intram_mem_option;
+ unsigned char res100[0x14];
+ unsigned int introm_mem_configuration;
+ unsigned int introm_mem_status;
+ unsigned int introm_mem_option;
+ unsigned char res101[0x14];
+ unsigned int jpeg_mem_configuration;
+ unsigned int jpeg_mem_status;
+ unsigned int jpeg_mem_option;
+ unsigned char res102[0x14];
+ unsigned int hsi_mem_configuration;
+ unsigned int hsi_mem_status;
+ unsigned int hsi_mem_option;
+ unsigned char res103[0x34];
+ unsigned int mcuiop_mem_configuration;
+ unsigned int mcuiop_mem_status;
+ unsigned int mcuiop_mem_option;
+ unsigned char res104[0x14];
+ unsigned int sata_mem_configuration;
+ unsigned int sata_mem_status;
+ unsigned int sata_mem_option;
+ unsigned char res105[0x34];
+ unsigned int pad_retention_dram_configuration;
+ unsigned int pad_retention_dram_status;
+ unsigned int pad_retention_dram_option;
+ unsigned char res106[0x14];
+ unsigned int pad_retention_mau_configuration;
+ unsigned int pad_retention_mau_status;
+ unsigned int pad_retention_mau_option;
+ unsigned char res107[0x14];
+ unsigned int pad_retention_jtag_configuration;
+ unsigned int pad_retention_jtag_status;
+ unsigned int pad_retention_jtag_option;
+ unsigned char res108[0x74];
+ unsigned int pad_retention_mmc2_configuration;
+ unsigned int pad_retention_mmc2_status;
+ unsigned int pad_retention_mmc2_option;
+ unsigned char res109[0x14];
+ unsigned int pad_retention_mmc3_configuration;
+ unsigned int pad_retention_mmc3_status;
+ unsigned int pad_retention_mmc3_option;
+ unsigned char res110[0x14];
+ unsigned int pad_retention_gpio_configuration;
+ unsigned int pad_retention_gpio_status;
+ unsigned int pad_retention_gpio_option;
+ unsigned char res111[0x14];
+ unsigned int pad_retention_uart_configuration;
+ unsigned int pad_retention_uart_status;
+ unsigned int pad_retention_uart_option;
+ unsigned char res112[0x14];
+ unsigned int pad_retention_mmc0_configuration;
+ unsigned int pad_retention_mmc0_status;
+ unsigned int pad_retention_mmc0_option;
+ unsigned char res113[0x14];
+ unsigned int pad_retention_mmc1_configuration;
+ unsigned int pad_retention_mmc1_status;
+ unsigned int pad_retention_mmc1_option;
+ unsigned char res114[0x14];
+ unsigned int pad_retention_ebia_configuration;
+ unsigned int pad_retention_ebia_status;
+ unsigned int pad_retention_ebia_option;
+ unsigned char res115[0x14];
+ unsigned int pad_retention_ebib_configuration;
+ unsigned int pad_retention_ebib_status;
+ unsigned int pad_retention_ebib_option;
+ unsigned char res116[0x14];
+ unsigned int pad_retention_spi_configuration;
+ unsigned int pad_retention_spi_status;
+ unsigned int pad_retention_spi_option;
+ unsigned char res117[0x14];
+ unsigned int pad_retention_gpio_dmc_configuration;
+ unsigned int pad_retention_gpio_dmc_status;
+ unsigned int pad_retention_gpio_dmc_option;
+ unsigned char res118[0x14];
+ unsigned int pad_isolation_configuration;
+ unsigned int pad_isolation_status;
+ unsigned int pad_isolation_option;
+ unsigned char res119[0x74];
+ unsigned int pad_isolation_dmc_configuration;
+ unsigned int pad_isolation_dmc_status;
+ unsigned int pad_isolation_dmc_option;
+ unsigned char res120[0x74];
+ unsigned int pad_alv_sel_configuration;
+ unsigned int pad_alv_sel_status;
+ unsigned int pad_alv_sel_option0;
+ unsigned int ps_hold_control;
+ unsigned char res130[0x110];
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned int xxti_option;
+ unsigned char res131[0x10];
+ unsigned int xxti_duration3;
+ unsigned char res132[0x1c0];
+ unsigned int ext_regulator_configuration;
+ unsigned int ext_regulator_status;
+ unsigned int ext_regulator_option;
+ unsigned char res133[0x10];
+ unsigned int ext_regulator_duration3;
+ unsigned char res134[0x1e0];
+ unsigned int gpio_mode_configuration;
+ unsigned int gpio_mode_status;
+ unsigned int gpio_mode_option;
+ unsigned char res135[0xf4];
+ unsigned int gpio_mode_dmc_configuration;
+ unsigned int gpio_mode_dmc_status;
+ unsigned int gpio_mode_dmc_option;
+ unsigned char res136[0xd4];
+ unsigned int gpio_mode_mau_configuration;
+ unsigned int gpio_mode_mau_status;
+ unsigned int gpio_mode_mau_option;
+ unsigned char res137[0x14];
+ unsigned int top_asb_reset_configuration;
+ unsigned int top_asb_reset_status;
+ unsigned int top_asb_reset_option;
+ unsigned char res138[0x14];
+ unsigned int top_asb_isolation_configuration;
+ unsigned int top_asb_isolation_status;
+ unsigned int top_asb_isolation_option;
+ unsigned char res139[0x5d4];
+ unsigned int gscl_configuration;
+ unsigned int gscl_status;
+ unsigned int gscl_option;
+ unsigned char res140[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res141[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res142[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res143[0x34];
+ unsigned int disp1_configuration;
+ unsigned int disp1_status;
+ unsigned int disp1_option;
+ unsigned char res144[0x14];
+ unsigned int mau_configuration;
+ unsigned int mau_status;
+ unsigned int mau_option;
+ unsigned char res145[0x334];
+ unsigned int cmu_clkstop_gscl_configuration;
+ unsigned int cmu_clkstop_gscl_status;
+ unsigned int cmu_clkstop_gscl_option;
+ unsigned char res146[0x14];
+ unsigned int cmu_clkstop_isp_configuration;
+ unsigned int cmu_clkstop_isp_status;
+ unsigned int cmu_clkstop_isp_option;
+ unsigned char res147[0x14];
+ unsigned int cmu_clkstop_mfc_configuration;
+ unsigned int cmu_clkstop_mfc_status;
+ unsigned int cmu_clkstop_mfc_option;
+ unsigned char res148[0x14];
+ unsigned int cmu_clkstop_g3d_configuration;
+ unsigned int cmu_clkstop_g3d_status;
+ unsigned int cmu_clkstop_g3d_option;
+ unsigned char res149[0x34];
+ unsigned int cmu_clkstop_disp1_configuration;
+ unsigned int cmu_clkstop_disp1_status;
+ unsigned int cmu_clkstop_disp1_option;
+ unsigned char res150[0x14];
+ unsigned int cmu_clkstop_mau_configuration;
+ unsigned int cmu_clkstop_mau_status;
+ unsigned int cmu_clkstop_mau_option;
+ unsigned char res151[0x134];
+ unsigned int cmu_sysclk_gscl_configuration;
+ unsigned int cmu_sysclk_gscl_status;
+ unsigned int cmu_sysclk_gscl_option;
+ unsigned char res152[0x18];
+ unsigned int cmu_sysclk_isp_status;
+ unsigned int cmu_sysclk_isp_option;
+ unsigned char res153[0x18];
+ unsigned int cmu_sysclk_mfc_status;
+ unsigned int cmu_sysclk_mfc_option;
+ unsigned char res154[0x18];
+ unsigned int cmu_sysclk_g3d_status;
+ unsigned int cmu_sysclk_g3d_option;
+ unsigned char res155[0x38];
+ unsigned int cmu_sysclk_disp1_status;
+ unsigned int cmu_sysclk_disp1_option;
+ unsigned char res156[0x18];
+ unsigned int cmu_sysclk_mau_status;
+ unsigned int cmu_sysclk_mau_option;
+ unsigned char res157[0x534];
+ unsigned int cmu_reset_gscl_configuration;
+ unsigned int cmu_reset_gscl_status;
+ unsigned int cmu_reset_gscl_option;
+ unsigned char res158[0x14];
+ unsigned int cmu_reset_isp_configuration;
+ unsigned int cmu_reset_isp_status;
+ unsigned int cmu_reset_isp_option;
+ unsigned char res159[0x14];
+ unsigned int cmu_reset_mfc_configuration;
+ unsigned int cmu_reset_mfc_status;
+ unsigned int cmu_reset_mfc_option;
+ unsigned char res160[0x14];
+ unsigned int cmu_reset_g3d_configuration;
+ unsigned int cmu_reset_g3d_status;
+ unsigned int cmu_reset_g3d_option;
+ unsigned char res161[0x34];
+ unsigned int cmu_reset_disp1_configuration;
+ unsigned int cmu_reset_disp1_status;
+ unsigned int cmu_reset_disp1_option;
+ unsigned char res162[0x14];
+ unsigned int cmu_reset_mau_configuration;
+ unsigned int cmu_reset_mau_status;
+ unsigned int cmu_reset_mau_option;
+ unsigned char res163[0x24];
+};
#endif /* __ASSEMBLY__ */
void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
--
1.7.4.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register
2012-05-02 13:52 ` [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register Rajeshwari Shinde
@ 2012-05-03 6:13 ` Chander Kashyap
2012-05-03 6:14 ` Chander Kashyap
0 siblings, 1 reply; 21+ messages in thread
From: Chander Kashyap @ 2012-05-03 6:13 UTC (permalink / raw)
To: u-boot
On 2 May 2012 19:22, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> This patch adds power mananagement register structure for exynos5 SoC.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> ?arch/arm/include/asm/arch-exynos/power.h | ?622 ++++++++++++++++++++++++++++++
> ?1 files changed, 622 insertions(+), 0 deletions(-)
>
Acked-by: Chander kashyap <chander.kashyap@linaro.org>
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register
2012-05-03 6:13 ` Chander Kashyap
@ 2012-05-03 6:14 ` Chander Kashyap
0 siblings, 0 replies; 21+ messages in thread
From: Chander Kashyap @ 2012-05-03 6:14 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari,
On 3 May 2012 11:43, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> On 2 May 2012 19:22, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
>> This patch adds power mananagement register structure for exynos5 SoC.
s/mananagement/management
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> ?arch/arm/include/asm/arch-exynos/power.h | ?622 ++++++++++++++++++++++++++++++
>> ?1 files changed, 622 insertions(+), 0 deletions(-)
>>
> Acked-by: Chander kashyap <chander.kashyap@linaro.org>
>
>
> --
> with warm regards,
> Chander Kashyap
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
2012-05-02 13:52 ` [U-Boot] [PATCH 1/5] exynos5: Add system register structure Rajeshwari Shinde
2012-05-02 13:52 ` [U-Boot] [PATCH 2/5] exynos5: Add structure for PMU register Rajeshwari Shinde
@ 2012-05-02 13:52 ` Rajeshwari Shinde
2012-05-03 7:33 ` Minkyu Kang
2012-05-02 13:52 ` [U-Boot] [PATCH 4/5] exynos5: usb: Fix incorrect USB base addresses Rajeshwari Shinde
` (2 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Rajeshwari Shinde @ 2012-05-02 13:52 UTC (permalink / raw)
To: u-boot
This patch adds functions to enable/disable the power of USB
host controller for exynos5.
This patch depends on the patch:
USB: S5P: Add ehci support.patch
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/power.c | 59 +++++++++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/power.h | 5 ++
arch/arm/include/asm/arch-exynos/sysreg.h | 1 +
drivers/usb/host/ehci-s5p.c | 3 +
4 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index c765304..a943219 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -24,6 +24,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/power.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sysreg.h>
static void exynos4_mipi_phy_control(unsigned int dev_index,
unsigned int enable)
@@ -52,3 +54,60 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
if (cpu_is_exynos4())
exynos4_mipi_phy_control(dev_index, enable);
}
+
+void exynos5_ps_hold_setup(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ /* Set PS-Hold high */
+ setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+void exynos5_enable_usb_phy(void)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+ unsigned int phy_cfg;
+
+ /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+ phy_cfg = readl(&sysreg->usb20_phy_cfg);
+ if (phy_cfg & USB20_PHY_CFG_EN) {
+ debug("USB 2.0 HOST link already selected\n");
+ } else {
+ phy_cfg |= USB20_PHY_CFG_EN;
+ writel(phy_cfg, &sysreg->usb20_phy_cfg);
+ }
+
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
+}
+
+void exynos5_disable_usb_phy(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ /* Disabling USBHost_PHY */
+ clrbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
+}
+
+void ps_hold_setup(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_ps_hold_setup();
+}
+
+void power_enable_usb_phy(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_enable_usb_phy();
+}
+
+void power_disable_usb_phy(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_disable_usb_phy();
+}
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 4236beb..4e2448b 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -855,4 +855,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
+#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
+#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
+void power_enable_usb_phy(void);
+void power_disable_usb_phy(void);
+
#endif
diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
index aca4b2b..2d8d35a 100644
--- a/arch/arm/include/asm/arch-exynos/sysreg.h
+++ b/arch/arm/include/asm/arch-exynos/sysreg.h
@@ -40,4 +40,5 @@ struct exynos5_sysreg {
};
#endif
+#define USB20_PHY_CFG_EN (1 << 0)
#endif
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 4dd4ec1..e575c48 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -30,6 +30,7 @@
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct s5p_usb_phy *usb)
{
+ power_enable_usb_phy();
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
@@ -70,6 +71,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb)
HOST_CTRL0_SIDDQ |
HOST_CTRL0_FORCESUSPEND |
HOST_CTRL0_FORCESLEEP);
+
+ power_disable_usb_phy();
}
/*
--
1.7.4.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI
2012-05-02 13:52 ` [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI Rajeshwari Shinde
@ 2012-05-03 7:33 ` Minkyu Kang
2012-05-03 12:52 ` Rajeshwari Birje
0 siblings, 1 reply; 21+ messages in thread
From: Minkyu Kang @ 2012-05-03 7:33 UTC (permalink / raw)
To: u-boot
On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> This patch adds functions to enable/disable the power of USB
> host controller for exynos5.
>
> This patch depends on the patch:
> USB: S5P: Add ehci support.patch
This is not a commit message.
Please move it under the "---" line.
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> ?arch/arm/cpu/armv7/exynos/power.c ? ? ? ? | ? 59 +++++++++++++++++++++++++++++
> ?arch/arm/include/asm/arch-exynos/power.h ?| ? ?5 ++
> ?arch/arm/include/asm/arch-exynos/sysreg.h | ? ?1 +
> ?drivers/usb/host/ehci-s5p.c ? ? ? ? ? ? ? | ? ?3 +
> ?4 files changed, 68 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
> index c765304..a943219 100644
> --- a/arch/arm/cpu/armv7/exynos/power.c
> +++ b/arch/arm/cpu/armv7/exynos/power.c
> @@ -24,6 +24,8 @@
> ?#include <common.h>
> ?#include <asm/io.h>
> ?#include <asm/arch/power.h>
> +#include <asm/arch/cpu.h>
cpu.h is already included.
please remove it.
> +#include <asm/arch/sysreg.h>
also you don't need this header file.. maybe.
>
> ?static void exynos4_mipi_phy_control(unsigned int dev_index,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned int enable)
> @@ -52,3 +54,60 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
> ? ? ? ?if (cpu_is_exynos4())
> ? ? ? ? ? ? ? ?exynos4_mipi_phy_control(dev_index, enable);
> ?}
> +
> +void exynos5_ps_hold_setup(void)
> +{
> + ? ? ? struct exynos5_power *power =
> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
> +
> + ? ? ? /* Set PS-Hold high */
> + ? ? ? setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);
> +}
> +
> +void exynos5_enable_usb_phy(void)
> +{
> + ? ? ? struct exynos5_sysreg *sysreg =
> + ? ? ? ? ? ? ? (struct exynos5_sysreg *)samsung_get_base_sysreg();
> + ? ? ? struct exynos5_power *power =
> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
> + ? ? ? unsigned int phy_cfg;
> +
> + ? ? ? /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
> + ? ? ? phy_cfg = readl(&sysreg->usb20_phy_cfg);
> + ? ? ? if (phy_cfg & USB20_PHY_CFG_EN) {
> + ? ? ? ? ? ? ? debug("USB 2.0 HOST link already selected\n");
Is it useful information for your debugging? just question :)
> + ? ? ? } else {
> + ? ? ? ? ? ? ? phy_cfg |= USB20_PHY_CFG_EN;
> + ? ? ? ? ? ? ? writel(phy_cfg, &sysreg->usb20_phy_cfg);
NAK.
The codes that are related with sysreg should be moved to system.c.
> + ? ? ? }
> +
> + ? ? ? /* Enabling USBHOST_PHY */
> + ? ? ? setbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
> +}
> +
> +void exynos5_disable_usb_phy(void)
> +{
> + ? ? ? struct exynos5_power *power =
> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
> +
> + ? ? ? /* Disabling USBHost_PHY */
> + ? ? ? clrbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
> +}
I think, you can combine enable/disable function to one.
> +
> +void ps_hold_setup(void)
> +{
> + ? ? ? if (cpu_is_exynos5())
> + ? ? ? ? ? ? ? exynos5_ps_hold_setup();
> +}
> +
> +void power_enable_usb_phy(void)
> +{
> + ? ? ? if (cpu_is_exynos5())
> + ? ? ? ? ? ? ? exynos5_enable_usb_phy();
> +}
> +
> +void power_disable_usb_phy(void)
> +{
> + ? ? ? if (cpu_is_exynos5())
> + ? ? ? ? ? ? ? exynos5_disable_usb_phy();
> +}
> diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
> index 4236beb..4e2448b 100644
> --- a/arch/arm/include/asm/arch-exynos/power.h
> +++ b/arch/arm/include/asm/arch-exynos/power.h
> @@ -855,4 +855,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
> ?#define EXYNOS_MIPI_PHY_SRESETN ? ? ? ? ? ? ? ?(1 << 1)
> ?#define EXYNOS_MIPI_PHY_MRESETN ? ? ? ? ? ? ? ?(1 << 2)
>
> +#define POWER_USB_HOST_PHY_CTRL_EN ? ? ? ? ? ? (1 << 0)
> +#define POWER_PS_HOLD_CONTROL_DATA_HIGH ? ? ? ? ? ? ? ?(1 << 8)
> +void power_enable_usb_phy(void);
> +void power_disable_usb_phy(void);
> +
> ?#endif
> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
> index aca4b2b..2d8d35a 100644
> --- a/arch/arm/include/asm/arch-exynos/sysreg.h
> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
> @@ -40,4 +40,5 @@ struct exynos5_sysreg {
> ?};
> ?#endif
>
> +#define USB20_PHY_CFG_EN ? ? ? (1 << 0)
> ?#endif
> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
> index 4dd4ec1..e575c48 100644
> --- a/drivers/usb/host/ehci-s5p.c
> +++ b/drivers/usb/host/ehci-s5p.c
> @@ -30,6 +30,7 @@
> ?/* Setup the EHCI host controller. */
> ?static void setup_usb_phy(struct s5p_usb_phy *usb)
> ?{
> + ? ? ? power_enable_usb_phy();
need space here.
and you should separate the function for power and system.
> ? ? ? ?clrbits_le32(&usb->usbphyctrl0,
> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FSEL_MASK |
> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_COMMONON_N |
> @@ -70,6 +71,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb)
> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_SIDDQ |
> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESUSPEND |
> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESLEEP);
> +
> + ? ? ? power_disable_usb_phy();
> ?}
>
> ?/*
> --
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI
2012-05-03 7:33 ` Minkyu Kang
@ 2012-05-03 12:52 ` Rajeshwari Birje
0 siblings, 0 replies; 21+ messages in thread
From: Rajeshwari Birje @ 2012-05-03 12:52 UTC (permalink / raw)
To: u-boot
Hi Minkyu,
Thank you for the comments.
On Thu, May 3, 2012 at 1:03 PM, Minkyu Kang <promsoft@gmail.com> wrote:
> On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
>> This patch adds functions to enable/disable the power of USB
>> host controller for exynos5.
>>
>> This patch depends on the patch:
>> USB: S5P: Add ehci support.patch
>
> This is not a commit message.
> Please move it under the "---" line.
--ok
>
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> ?arch/arm/cpu/armv7/exynos/power.c ? ? ? ? | ? 59 +++++++++++++++++++++++++++++
>> ?arch/arm/include/asm/arch-exynos/power.h ?| ? ?5 ++
>> ?arch/arm/include/asm/arch-exynos/sysreg.h | ? ?1 +
>> ?drivers/usb/host/ehci-s5p.c ? ? ? ? ? ? ? | ? ?3 +
>> ?4 files changed, 68 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
>> index c765304..a943219 100644
>> --- a/arch/arm/cpu/armv7/exynos/power.c
>> +++ b/arch/arm/cpu/armv7/exynos/power.c
>> @@ -24,6 +24,8 @@
>> ?#include <common.h>
>> ?#include <asm/io.h>
>> ?#include <asm/arch/power.h>
>> +#include <asm/arch/cpu.h>
>
> cpu.h is already included.
> please remove it.
--- will do so
>
>> +#include <asm/arch/sysreg.h>
>
> also you don't need this header file.. maybe.
-- will remove this header file.
>
>>
>> ?static void exynos4_mipi_phy_control(unsigned int dev_index,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned int enable)
>> @@ -52,3 +54,60 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
>> ? ? ? ?if (cpu_is_exynos4())
>> ? ? ? ? ? ? ? ?exynos4_mipi_phy_control(dev_index, enable);
>> ?}
>> +
>> +void exynos5_ps_hold_setup(void)
>> +{
>> + ? ? ? struct exynos5_power *power =
>> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
>> +
>> + ? ? ? /* Set PS-Hold high */
>> + ? ? ? setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);
>> +}
>> +
>> +void exynos5_enable_usb_phy(void)
>> +{
>> + ? ? ? struct exynos5_sysreg *sysreg =
>> + ? ? ? ? ? ? ? (struct exynos5_sysreg *)samsung_get_base_sysreg();
>> + ? ? ? struct exynos5_power *power =
>> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
>> + ? ? ? unsigned int phy_cfg;
>> +
>> + ? ? ? /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
>> + ? ? ? phy_cfg = readl(&sysreg->usb20_phy_cfg);
>> + ? ? ? if (phy_cfg & USB20_PHY_CFG_EN) {
>> + ? ? ? ? ? ? ? debug("USB 2.0 HOST link already selected\n");
>
> Is it useful information for your debugging? just question :)
-- will remove the same :)
>
>> + ? ? ? } else {
>> + ? ? ? ? ? ? ? phy_cfg |= USB20_PHY_CFG_EN;
>> + ? ? ? ? ? ? ? writel(phy_cfg, &sysreg->usb20_phy_cfg);
>
> NAK.
> The codes that are related with sysreg should be moved to system.c.
-- will correct this
>
>> + ? ? ? }
>> +
>> + ? ? ? /* Enabling USBHOST_PHY */
>> + ? ? ? setbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
>> +}
>> +
>> +void exynos5_disable_usb_phy(void)
>> +{
>> + ? ? ? struct exynos5_power *power =
>> + ? ? ? ? ? ? ? (struct exynos5_power *)samsung_get_base_power();
>> +
>> + ? ? ? /* Disabling USBHost_PHY */
>> + ? ? ? clrbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN);
>> +}
>
> I think, you can combine enable/disable function to one.
-- ok
>
>> +
>> +void ps_hold_setup(void)
>> +{
>> + ? ? ? if (cpu_is_exynos5())
>> + ? ? ? ? ? ? ? exynos5_ps_hold_setup();
>> +}
>> +
>> +void power_enable_usb_phy(void)
>> +{
>> + ? ? ? if (cpu_is_exynos5())
>> + ? ? ? ? ? ? ? exynos5_enable_usb_phy();
>> +}
>> +
>> +void power_disable_usb_phy(void)
>> +{
>> + ? ? ? if (cpu_is_exynos5())
>> + ? ? ? ? ? ? ? exynos5_disable_usb_phy();
>> +}
>> diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
>> index 4236beb..4e2448b 100644
>> --- a/arch/arm/include/asm/arch-exynos/power.h
>> +++ b/arch/arm/include/asm/arch-exynos/power.h
>> @@ -855,4 +855,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
>> ?#define EXYNOS_MIPI_PHY_SRESETN ? ? ? ? ? ? ? ?(1 << 1)
>> ?#define EXYNOS_MIPI_PHY_MRESETN ? ? ? ? ? ? ? ?(1 << 2)
>>
>> +#define POWER_USB_HOST_PHY_CTRL_EN ? ? ? ? ? ? (1 << 0)
>> +#define POWER_PS_HOLD_CONTROL_DATA_HIGH ? ? ? ? ? ? ? ?(1 << 8)
>> +void power_enable_usb_phy(void);
>> +void power_disable_usb_phy(void);
>> +
>> ?#endif
>> diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h
>> index aca4b2b..2d8d35a 100644
>> --- a/arch/arm/include/asm/arch-exynos/sysreg.h
>> +++ b/arch/arm/include/asm/arch-exynos/sysreg.h
>> @@ -40,4 +40,5 @@ struct exynos5_sysreg {
>> ?};
>> ?#endif
>>
>> +#define USB20_PHY_CFG_EN ? ? ? (1 << 0)
>> ?#endif
>> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
>> index 4dd4ec1..e575c48 100644
>> --- a/drivers/usb/host/ehci-s5p.c
>> +++ b/drivers/usb/host/ehci-s5p.c
>> @@ -30,6 +30,7 @@
>> ?/* Setup the EHCI host controller. */
>> ?static void setup_usb_phy(struct s5p_usb_phy *usb)
>> ?{
>> + ? ? ? power_enable_usb_phy();
>
> need space here.
> and you should separate the function for power and system.
-- ok
>
>> ? ? ? ?clrbits_le32(&usb->usbphyctrl0,
>> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FSEL_MASK |
>> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_COMMONON_N |
>> @@ -70,6 +71,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb)
>> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_SIDDQ |
>> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESUSPEND |
>> ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESLEEP);
>> +
>> + ? ? ? power_disable_usb_phy();
>> ?}
>>
>> ?/*
>> --
>
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Regards,
Rajeshwari Shinde.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/5] exynos5: usb: Fix incorrect USB base addresses
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
` (2 preceding siblings ...)
2012-05-02 13:52 ` [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI Rajeshwari Shinde
@ 2012-05-02 13:52 ` Rajeshwari Shinde
2012-05-03 6:15 ` Chander Kashyap
2012-05-02 13:52 ` [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250 Rajeshwari Shinde
2012-05-03 1:49 ` [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Kyungmin Park
5 siblings, 1 reply; 21+ messages in thread
From: Rajeshwari Shinde @ 2012-05-02 13:52 UTC (permalink / raw)
To: u-boot
This patch corrects the base addresses for USB_PHY and USB_OTG.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/include/asm/arch-exynos/cpu.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ac4ddc7..891970d 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -68,10 +68,10 @@
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
+#define EXYNOS5_USBPHY_BASE 0x12130000
+#define EXYNOS5_USBOTG_BASE 0x12140000
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_SROMC_BASE 0x12250000
-#define EXYNOS5_USBOTG_BASE 0x12480000
-#define EXYNOS5_USBPHY_BASE 0x12480000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
--
1.7.4.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
` (3 preceding siblings ...)
2012-05-02 13:52 ` [U-Boot] [PATCH 4/5] exynos5: usb: Fix incorrect USB base addresses Rajeshwari Shinde
@ 2012-05-02 13:52 ` Rajeshwari Shinde
2012-05-03 6:43 ` Chander Kashyap
2012-05-03 7:38 ` Minkyu Kang
2012-05-03 1:49 ` [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Kyungmin Park
5 siblings, 2 replies; 21+ messages in thread
From: Rajeshwari Shinde @ 2012-05-02 13:52 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/include/asm/arch-exynos/cpu.h | 1 +
include/configs/smdk5250.h | 6 ++++++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 891970d..17f8fe3 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -68,6 +68,7 @@
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5_USBPHY_BASE 0x12130000
#define EXYNOS5_USBOTG_BASE 0x12140000
#define EXYNOS5_MMC_BASE 0x12200000
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 9659f9e..84c7ce8 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -101,6 +101,12 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_S5P
+#define CONFIG_USB_STORAGE
+
/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
--
1.7.4.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250
2012-05-02 13:52 ` [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250 Rajeshwari Shinde
@ 2012-05-03 6:43 ` Chander Kashyap
2012-05-03 7:38 ` Minkyu Kang
1 sibling, 0 replies; 21+ messages in thread
From: Chander Kashyap @ 2012-05-03 6:43 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari,
On 2 May 2012 19:22, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> ?arch/arm/include/asm/arch-exynos/cpu.h | ? ?1 +
> ?include/configs/smdk5250.h ? ? ? ? ? ? | ? ?6 ++++++
> ?2 files changed, 7 insertions(+), 0 deletions(-)
>
Acked-by: Chander kashyap <chander.kashyap@linaro.org>
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250
2012-05-02 13:52 ` [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250 Rajeshwari Shinde
2012-05-03 6:43 ` Chander Kashyap
@ 2012-05-03 7:38 ` Minkyu Kang
2012-05-03 12:06 ` Rajeshwari Birje
1 sibling, 1 reply; 21+ messages in thread
From: Minkyu Kang @ 2012-05-03 7:38 UTC (permalink / raw)
To: u-boot
On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> ?arch/arm/include/asm/arch-exynos/cpu.h | ? ?1 +
> ?include/configs/smdk5250.h ? ? ? ? ? ? | ? ?6 ++++++
> ?2 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
> index 891970d..17f8fe3 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -68,6 +68,7 @@
> ?#define EXYNOS5_DMC_CTRL_BASE ? ? ? ? ?0x10DD0000
> ?#define EXYNOS5_GPIO_PART1_BASE ? ? ? ? ? ? ? ?0x11400000
> ?#define EXYNOS5_MIPI_DSIM_BASE ? ? ? ? 0x11D00000
> +#define EXYNOS5_USB_HOST_EHCI_BASE ? ? 0x12110000
Unrelated change.
maybe this should be move into "Add ehci support" patch?
> ?#define EXYNOS5_USBPHY_BASE ? ? ? ? ? ?0x12130000
> ?#define EXYNOS5_USBOTG_BASE ? ? ? ? ? ?0x12140000
> ?#define EXYNOS5_MMC_BASE ? ? ? ? ? ? ? 0x12200000
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250
2012-05-03 7:38 ` Minkyu Kang
@ 2012-05-03 12:06 ` Rajeshwari Birje
0 siblings, 0 replies; 21+ messages in thread
From: Rajeshwari Birje @ 2012-05-03 12:06 UTC (permalink / raw)
To: u-boot
Hi Minkyu,
Thank you for the comments.
On Thu, May 3, 2012 at 1:08 PM, Minkyu Kang <promsoft@gmail.com> wrote:
> On 2 May 2012 22:52, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> ?arch/arm/include/asm/arch-exynos/cpu.h | ? ?1 +
>> ?include/configs/smdk5250.h ? ? ? ? ? ? | ? ?6 ++++++
>> ?2 files changed, 7 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
>> index 891970d..17f8fe3 100644
>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>> @@ -68,6 +68,7 @@
>> ?#define EXYNOS5_DMC_CTRL_BASE ? ? ? ? ?0x10DD0000
>> ?#define EXYNOS5_GPIO_PART1_BASE ? ? ? ? ? ? ? ?0x11400000
>> ?#define EXYNOS5_MIPI_DSIM_BASE ? ? ? ? 0x11D00000
>> +#define EXYNOS5_USB_HOST_EHCI_BASE ? ? 0x12110000
>
> Unrelated change.
> maybe this should be move into "Add ehci support" patch?
-- will add the same in "Add ehci support" patch.
>
>> ?#define EXYNOS5_USBPHY_BASE ? ? ? ? ? ?0x12130000
>> ?#define EXYNOS5_USBOTG_BASE ? ? ? ? ? ?0x12140000
>> ?#define EXYNOS5_MMC_BASE ? ? ? ? ? ? ? 0x12200000
>
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Regards,
Rajeshwari Shinde.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support
2012-05-02 13:52 [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Rajeshwari Shinde
` (4 preceding siblings ...)
2012-05-02 13:52 ` [U-Boot] [PATCH 5/5] exynos5: usb: Enable USB 2.0 on smdk5250 Rajeshwari Shinde
@ 2012-05-03 1:49 ` Kyungmin Park
2012-05-03 2:46 ` Marek Vasut
5 siblings, 1 reply; 21+ messages in thread
From: Kyungmin Park @ 2012-05-03 1:49 UTC (permalink / raw)
To: u-boot
Hi,
Can you share the purpose of USB host support at bootloader?
Just curious.
Thank you,
Kyungmin Park
On 5/2/12, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> This patchset series adds support to enable USB 2.0 on smdk5250.
> It includes addition of system and power management registers,
> functions to enable and disable power to the USB host controller.
>
> This patchset is based on:
> USB: S5P: Add ehci support.patch
>
> Rajeshwari Shinde (5):
> exynos5: Add system register structure
> exynos5: Add structure for PMU register
> exynos5: Add power Enable/Disable for USB-EHCI
> exynos5: usb: Fix incorrect USB base addresses
> exynos5: usb: Enable USB 2.0 on smdk5250
>
> arch/arm/cpu/armv7/exynos/power.c | 59 +++
> arch/arm/include/asm/arch-exynos/cpu.h | 5 +-
> arch/arm/include/asm/arch-exynos/power.h | 627
> +++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-exynos/sysreg.h | 44 ++
> drivers/usb/host/ehci-s5p.c | 3 +
> include/configs/smdk5250.h | 6 +
> 6 files changed, 742 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
>
> --
> 1.7.4.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support
2012-05-03 1:49 ` [U-Boot] [PATCH 0/5] exynos5: usb: Enable USB 2.0 support Kyungmin Park
@ 2012-05-03 2:46 ` Marek Vasut
0 siblings, 0 replies; 21+ messages in thread
From: Marek Vasut @ 2012-05-03 2:46 UTC (permalink / raw)
To: u-boot
Dear Kyungmin Park,
> Hi,
>
> Can you share the purpose of USB host support at bootloader?
You can boot the system completely off a USB stick ...
>
> Just curious.
>
> Thank you,
> Kyungmin Park
>
> On 5/2/12, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> > This patchset series adds support to enable USB 2.0 on smdk5250.
> > It includes addition of system and power management registers,
> > functions to enable and disable power to the USB host controller.
> >
> > This patchset is based on:
> > USB: S5P: Add ehci support.patch
> >
> > Rajeshwari Shinde (5):
> > exynos5: Add system register structure
> > exynos5: Add structure for PMU register
> > exynos5: Add power Enable/Disable for USB-EHCI
> > exynos5: usb: Fix incorrect USB base addresses
> > exynos5: usb: Enable USB 2.0 on smdk5250
> >
> > arch/arm/cpu/armv7/exynos/power.c | 59 +++
> > arch/arm/include/asm/arch-exynos/cpu.h | 5 +-
> > arch/arm/include/asm/arch-exynos/power.h | 627
> >
> > +++++++++++++++++++++++++++++
> >
> > arch/arm/include/asm/arch-exynos/sysreg.h | 44 ++
> > drivers/usb/host/ehci-s5p.c | 3 +
> > include/configs/smdk5250.h | 6 +
> > 6 files changed, 742 insertions(+), 2 deletions(-)
> > create mode 100644 arch/arm/include/asm/arch-exynos/sysreg.h
> >
> > --
> > 1.7.4.4
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 21+ messages in thread