From mboxrd@z Thu Jan 1 00:00:00 1970 From: Allen Martin Date: Wed, 6 Jun 2012 12:37:20 -0700 Subject: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target In-Reply-To: <4FCF89D7.2060404@wwwdotorg.org> References: <1338931225-12246-1-git-send-email-amartin@nvidia.com> <1338931225-12246-9-git-send-email-amartin@nvidia.com> <4FCF89D7.2060404@wwwdotorg.org> Message-ID: <20120606193719.GG13311@nvidia.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote: > On 06/05/2012 03:20 PM, Allen Martin wrote: > > Add target for tegra20 u-boot image. This is a concatenation of tegra > > spl and normal u-boot binaries. > > > diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk > > > +PAD_TO=0x00108000 > > Oh crap, does this mean that we have to start flashing the combined > u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier > patch) instead of 0x108000? That would cause all kinds of problems. If > that is the case, can we move the SPL to the existing 0x108000, and bump > the regular U-Boot up a bit to make space? If that isn't the case, could > you please explain exactly how the SPL memory layout etc. works for me? > Thanks. The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the existing 0x108000 for the normal u-boot but it doesn't have to be that way. The only requirement is that the SPL needs to know the address of the normal u-boot at compile time because it doesn't have any smarts to look for it. I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable. -Allen -- nvpublic