From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sat, 16 Jun 2012 00:29:23 +0200 Subject: [U-Boot] [PATCH] ARM: support for cache coherent allocations In-Reply-To: <1338414113-25281-1-git-send-email-ilya.yanok@cogentembedded.com> References: <1338414113-25281-1-git-send-email-ilya.yanok@cogentembedded.com> Message-ID: <201206160029.23925.marek.vasut@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Ilya Yanok, > This is a draft implementation of cache coherent memory allocator. > This simple implementation just reserves memory area below malloc > space and leave it uncached even if data cache is enabled. > Allocations are even simpler: code just verifies that we have > enough space and increments the offset counter. No deallocations > supported for now. In future versions we could probably use > dlmalloc allocator to get space out of coherent pool. > > Signed-off-by: Ilya Yanok Hm, can't we just punch a hole in the MMU table at runtime instead of preallocating it like this? Also, what is this for? Can we not simply flush/invalidate the caches? Best regards, Marek Vasut