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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned
Date: Tue, 26 Jun 2012 01:37:31 +0200	[thread overview]
Message-ID: <201206260137.31646.marex@denx.de> (raw)
In-Reply-To: <4FE898A2.9060801@freescale.com>

Dear Scott Wood,

> On 06/24/2012 07:17 PM, Marek Vasut wrote:
> > This prevents the scenario where data cache is on and the
> > device uses DMA to deploy data. In that case, it might not
> > be possible to flush/invalidate data to RAM properly. The
> > other option is to use bounce buffer,
> 
> Or get cache coherent hardware. :-)

Oh ... you mean powerpc? Or rather something like this 
http://cache.freescale.com/files/32bit/doc/fact_sheet/QORIQLS2FAMILYFS.pdf ? :-D

> > but that involves a lot of copying and therefore degrades performance
> > rapidly. Therefore disallow this possibility of unaligned load
> > address altogether if data cache is on.
> 
> How about use the bounce buffer only if the address is misaligned?

Not happening, bounce buffer is bullshit, especially if we can prevent it by 
teaching user not to do retarded things.

It's like driving a car in the wrong lane. Sure, you can do it, but it'll 
eventually have some consequences. And using a bounce buffer is like driving a 
tank in the wrong lane ...

> The
> corrective action a user has to take is the same as with this patch,
> except for an additional option of living with the slight performance
> penalty.

Slight is very weak word here.

> How often does this actually happen?  How much does it
> actually slow things down compared to the speed of the NAND chip?

If the user is dumb, always. But if you tell the user how to milk the most of 
the hardware, he'll be happier.

> I'm hesitant to break something -- even if it's odd (literally in this
> case) -- that currently works on most hardware, just because one or two
> drivers can't handle it.  It feels kind of like changing the read() and
> write() system calls to require cacheline alignment. :-P

That's actually almost right, we're doing a bootloader here, it might have 
limitations. We're not writing yet another operating system with no bounds on 
possibilities!

> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Scott Wood <scottwood@freescale.com>
> > ---
> > 
> >  common/cmd_nand.c |    9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/common/cmd_nand.c b/common/cmd_nand.c
> > index a91ccf4..122a91c 100644
> > --- a/common/cmd_nand.c
> > +++ b/common/cmd_nand.c
> > @@ -609,6 +609,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc,
> > char * const argv[])
> > 
> >  			goto usage;
> >  		
> >  		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
> > 
> > +		if (!cacheline_aligned(addr))
> > +			return 1;
> 
> There's no way you can just return like this without printing an error
> that lets the user know that the operation wasn't performed, and why.
> 
> -Scott

Best regards,
Marek Vasut

  parent reply	other threads:[~2012-06-25 23:37 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-25  0:17 [U-Boot] [PATCH 0/9] CACHE: Finishing touches Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 1/9] COMMON: Add __stringify() function Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 2/9] CACHE: Add cache_aligned() macro Marek Vasut
2012-06-25 21:12   ` Scott Wood
2012-06-25 23:30     ` Marek Vasut
2012-07-07  3:00       ` Aneesh V
2012-06-25  0:17 ` [U-Boot] [PATCH 3/9] CACHE: ext2load: Test if start address is aligned Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 4/9] CACHE: fatload: " Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 5/9] CACHE: mmc read/write: " Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 6/9] CACHE: nand " Marek Vasut
2012-06-25 16:58   ` Scott Wood
2012-06-25 18:43     ` Tom Rini
2012-06-25 20:08       ` Scott Wood
2012-06-25 20:48         ` Tom Rini
2012-06-25 21:17           ` Scott Wood
2012-06-25 21:22             ` Tom Rini
2012-06-25 23:42             ` Marek Vasut
2012-06-26  0:37               ` Scott Wood
2012-06-26  1:16                 ` Marek Vasut
2012-06-26 19:38                   ` Scott Wood
2012-06-25 23:38       ` Marek Vasut
2012-06-25 23:37     ` Marek Vasut [this message]
2012-06-25 23:57       ` Scott Wood
2012-06-26  1:33         ` Marek Vasut
2012-06-26 19:25           ` Scott Wood
2012-06-26 20:39             ` Marek Vasut
2012-07-07  3:05   ` Aneesh V
2012-06-25  0:17 ` [U-Boot] [PATCH 7/9] CACHE: net: " Marek Vasut
2012-06-25 18:05   ` Joe Hershberger
2012-06-25 23:16     ` Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 8/9] CACHE: net: asix: Fix asix driver to work with data cache on Marek Vasut
2012-06-25 18:07   ` Joe Hershberger
2012-06-25 23:16     ` Marek Vasut
2012-07-06 23:09     ` Marek Vasut
2012-07-06 23:16       ` Marek Vasut
2012-06-25  0:17 ` [U-Boot] [PATCH 9/9] M28EVK: Enable instruction and data cache Marek Vasut

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