From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Sun, 8 Jul 2012 23:31:28 +0200
Subject: [U-Boot] [PATCH] smsc95xx: align buffers to cache line size
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References: <1341755583-30090-1-git-send-email-ilya.yanok@cogentembedded.com>
	<201207082059.32988.marek.vasut@gmail.com>
	<CAA3CPjVuizzK-_bh+pxET4WmoyKJyaLsNWfSdftfLxfRYULPZw@mail.gmail.com>
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Dear Ilya Yanok,

> Dear Marek,
> 
> On Sun, Jul 8, 2012 at 10:59 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
> > btw. this will fail with cache line < 32 .
> 
> Hm.. I have to admit I'm not very much into USB specs and I don't have any
> non-ARMv7 system now to do some testing...
> But it used to work without any alignment, right? (with disabled dcache, of
> course)
> That makes me think that data buffers don't need any alignment (from USB
> pov, not cache) and 32-byte alignment is required for internal structs
> only.

See ehci-r10.pdf ... chapter 3.5 ... the buffer pointer has to be aligned too it 
seems.

> Regards, Ilya.

Best regards,
Marek Vasut