[U-Boot] [PATCH] smsc95xx: align buffers to cache line size

[Marek Vasut <marek.vasut@gmail.com>]

Dear Ilya Yanok,

> Hi Marek,
> 
> On Tue, Jul 10, 2012 at 6:17 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> > > Well, of course we need proper alignment for cache stuff (well,
> > > actually
> > 
> > we
> > 
> > > can skip this alignment thing for the buffer we will flush as long as
> > > all buffers we are going to invalidate are properly aligned/sized...
> > > but
> > 
> > that's
> > 
> > > too tricky, personally I'd prefer every DMAed buffer to be cache-line
> > > aligned/sized).
> > > 
> > > And this patch actually adds the alignment for the smsc95xx driver's
> > > buffers. In your initial reply you said it will be broken on systems
> > > with ARCH_DMA_MINALIGN < 32, so I'm asking what makes you think so?
> > 
> > ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be
> > aligned to
> > 16 bytes for arch with 16 byte cachelines.
> 
> Yes, and this is exactly what we need.

It isn't, EHCI needs it aligned on 32 byte boundary.

> Regards, Ilya.

Best regards,
Marek Vasut