From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Tue, 10 Jul 2012 11:34:09 +0200
Subject: [U-Boot] [PATCH] smsc95xx: align buffers to cache line size
In-Reply-To: <CAA3CPjXiekVdR=XMy84KMiaXKLW1h9+aSPfSFn+gR8oXiLqxDA@mail.gmail.com>
References: <1341755583-30090-1-git-send-email-ilya.yanok@cogentembedded.com>
	<201207100417.14740.marek.vasut@gmail.com>
	<CAA3CPjXiekVdR=XMy84KMiaXKLW1h9+aSPfSFn+gR8oXiLqxDA@mail.gmail.com>
Message-ID: <201207101134.09540.marek.vasut@gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Dear Ilya Yanok,

> Hi Marek,
> 
> On Tue, Jul 10, 2012 at 6:17 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> > > Well, of course we need proper alignment for cache stuff (well,
> > > actually
> > 
> > we
> > 
> > > can skip this alignment thing for the buffer we will flush as long as
> > > all buffers we are going to invalidate are properly aligned/sized...
> > > but
> > 
> > that's
> > 
> > > too tricky, personally I'd prefer every DMAed buffer to be cache-line
> > > aligned/sized).
> > > 
> > > And this patch actually adds the alignment for the smsc95xx driver's
> > > buffers. In your initial reply you said it will be broken on systems
> > > with ARCH_DMA_MINALIGN < 32, so I'm asking what makes you think so?
> > 
> > ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be
> > aligned to
> > 16 bytes for arch with 16 byte cachelines.
> 
> Yes, and this is exactly what we need.

It isn't, EHCI needs it aligned on 32 byte boundary.

> Regards, Ilya.

Best regards,
Marek Vasut