From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurence Withers Date: Mon, 30 Jul 2012 16:34:39 +0000 Subject: [U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed In-Reply-To: <1343665815-25606-3-git-send-email-lwithers@guralp.com> References: <1343665815-25606-1-git-send-email-lwithers@guralp.com> <1343665815-25606-3-git-send-email-lwithers@guralp.com> Message-ID: <20120730163439.GC26574@guralp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Jul 30, 2012 at 04:30:15PM +0000, Laurence Withers wrote: > Replace a magic number for the DDR2/mDDR PHY clock ID with a proper > definition. In addition, don't request this clock ID on DA830 hardware, > which does not have a DDR2/mDDR PHY (or associated PLL controller). > > Signed-off-by: Laurence Withers > Cc: Prabhakar Lad > --- > arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- > arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ > 2 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c > index 4bdb08b..b31add8 100644 > --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c > +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c > @@ -122,7 +122,8 @@ int set_cpu_clk_info(void) > { > gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; > /* DDR PHY uses an x2 input clock */ > - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; > + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : > + (clk_get(DAVINCI_DDR_CLKID) / 1000000); > gd->bd->bi_dsp_freq = 0; > return 0; > } > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h > index 0fce940..7f3dcc2 100644 > --- a/arch/arm/include/asm/arch-davinci/hardware.h > +++ b/arch/arm/include/asm/arch-davinci/hardware.h > @@ -459,10 +459,12 @@ enum davinci_clk_ids { > DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, > DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, > DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, > + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, > DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, > > /* map peripherals to clock IDs */ > DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, > + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, > DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, > DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, > DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, > -- > 1.7.2.5 > Hi, This patch does depend on my earlier patch to tidy up the definition of set_cpu_clk_info() : http://lists.denx.de/pipermail/u-boot/2012-July/129205.html Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+443333408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM