From: Tom Rini <trini@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs
Date: Fri, 3 Aug 2012 09:06:43 -0700 [thread overview]
Message-ID: <20120803160643.GF16633@bill-the-cat> (raw)
In-Reply-To: <1343727037-17419-1-git-send-email-lwithers@guralp.com>
On Tue, Jul 31, 2012 at 09:30:33AM +0000, Laurence Withers wrote:
> This small series of patches tidies up the clock IDs that are used to interact
> with the PLL controllers on the DaVinci DA8xx processors.
>
> It more clearly defines the structure and meaning of the IDs and untangles some
> model-specific code that can't be shared among the family. This tidying allows
> three bugs to be identified and resolved:
> - on the DA850, UART2's clock may come from ASYNC3, unlike the DA830;
> - the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it;
> - the DSP speed reported by bdinfo was not being initialised on the DA8xx
> family.
>
> Laurence Withers (4):
> DaVinci DA8xx: tidy up clock ID definition
> DaVinci DA850: UART2 clock ID comes from ASYNC3
> DaVinci DA8xx: replace magic number for DDR speed
> DaVinci DA8xx: fix set_cpu_clk_info()
Applied to u-boot-ti/master, thanks!
--
Tom
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prev parent reply other threads:[~2012-08-03 16:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-31 9:30 [U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs Laurence Withers
2012-07-31 9:30 ` [U-Boot] [PATCH v2 1/4] DaVinci DA8xx: tidy up clock ID definition Laurence Withers
2012-08-03 16:05 ` Tom Rini
2012-07-31 9:30 ` [U-Boot] [PATCH v2 2/4] DaVinci DA850: UART2 clock ID comes from ASYNC3 Laurence Withers
2012-08-03 16:06 ` Tom Rini
2012-07-31 9:30 ` [U-Boot] [PATCH v2 3/4] DaVinci DA8xx: replace magic number for DDR speed Laurence Withers
2012-07-31 9:30 ` [U-Boot] [PATCH v2 4/4] DaVinci DA8xx: fix set_cpu_clk_info() Laurence Withers
2012-08-01 5:24 ` [U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs Prabhakar Lad
2012-08-03 16:06 ` Tom Rini [this message]
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