From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 17 Aug 2012 22:50:40 +0200 Subject: [U-Boot] [PATCH 2/3] pxa25x: Add UDC registers definitions In-Reply-To: <1345235499-32556-2-git-send-email-luk0104@gmail.com> References: <1345235499-32556-1-git-send-email-luk0104@gmail.com> <1345235499-32556-2-git-send-email-luk0104@gmail.com> Message-ID: <201208172250.40321.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear ?ukasz Da?ek, > Signed-off-by: ?ukasz Da?ek > --- > arch/arm/include/asm/arch-pxa/regs-usb.h | 174 > ++++++++++++++++++++++++++++++ 1 files changed, 174 insertions(+), 0 > deletions(-) > create mode 100644 arch/arm/include/asm/arch-pxa/regs-usb.h > > diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h > b/arch/arm/include/asm/arch-pxa/regs-usb.h new file mode 100644 > index 0000000..8e4a4a4 > --- /dev/null > +++ b/arch/arm/include/asm/arch-pxa/regs-usb.h > @@ -0,0 +1,174 @@ > +/* > + * PXA25x UDC definitions > + * > + * Copyright (C) ?ukasz Da?ek > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 > USA + */ > + > +#ifndef __REGS_USB_H__ > +#define __REGS_USB_H__ > + > +#include Drop this include, see below. > +struct pxa25x_udc_regs { > + > + /* UDC Control Register */ > + uint32_t udccr; /* 0x000 */ > + uint8_t reserved1[4]; Make it uint32_t and you're done with the array ;-) > + > + /* UDC Control Function Register */ > + uint32_t udccfr; /* 0x008 */ > + uint8_t reserved2[4]; Ditto > + /* UDC Endpoint Control/Status Registers */ > + uint32_t udccs0; /* 0x010 */ > + uint32_t udccs1; /* 0x014 */ > + uint32_t udccs2; /* 0x018 */ > + uint32_t udccs3; /* 0x01c */ > + uint32_t udccs4; /* 0x020 */ > + uint32_t udccs5; /* 0x024 */ > + uint32_t udccs6; /* 0x028 */ > + uint32_t udccs7; /* 0x02c */ > + uint32_t udccs8; /* 0x030 */ > + uint32_t udccs9; /* 0x034 */ > + uint32_t udccs10; /* 0x038 */ > + uint32_t udccs11; /* 0x03c */ > + uint32_t udccs12; /* 0x040 */ > + uint32_t udccs13; /* 0x044 */ > + uint32_t udccs14; /* 0x048 */ > + uint32_t udccs15; /* 0x04c */ Use array here maybe? ;-) > + /* UDC Interrupt Control/Status Registers */ > + uint32_t uicr0; /* 0x050 */ > + uint32_t uicr1; /* 0x054 */ > + uint32_t usir0; /* 0x058 */ > + uint32_t usir1; /* 0x05c */ > + > + /* UDC Frame Number/Byte Count Registers */ > + uint32_t ufnrh; /* 0x060 */ > + uint32_t ufnrl; /* 0x064 */ > + uint32_t ubcr2; /* 0x068 */ > + uint32_t ubcr4; /* 0x06c */ > + uint32_t ubcr7; /* 0x070 */ > + uint32_t ubcr9; /* 0x074 */ > + uint32_t ubcr12; /* 0x078 */ > + uint32_t ubcr14; /* 0x07c */ > + > + /* UDC Endpoint Data Registers */ > + uint32_t uddr0; /* 0x080 */ > + uint8_t reserved3[28]; Same here, trim it to uint32_t > + uint32_t uddr5; /* 0x0a0 */ > + uint8_t reserved4[28]; > + uint32_t uddr10; /* 0x0c0 */ > + uint8_t reserved5[28]; > + uint32_t uddr15; /* 0x0e0 */ > + uint8_t reserved6[28]; > + uint32_t uddr1; /* 0x100 */ > + uint8_t reserved7[124]; > + uint32_t uddr2; /* 0x180 */ > + uint8_t reserved8[124]; > + uint32_t uddr3; /* 0x200 */ > + uint8_t reserved9[508]; > + uint32_t uddr4; /* 0x400 */ > + uint8_t reserved10[508]; > + uint32_t uddr6; /* 0x600 */ > + uint8_t reserved11[124]; > + uint32_t uddr7; /* 0x680 */ > + uint8_t reserved12[124]; > + uint32_t uddr8; /* 0x700 */ > + uint8_t reserved13[508]; > + uint32_t uddr9; /* 0x900 */ > + uint8_t reserved14[508]; > + uint32_t uddr11; /* 0xb00 */ > + uint8_t reserved15[124]; > + uint32_t uddr12; /* 0xb80 */ > + uint8_t reserved16[124]; > + uint32_t uddr13; /* 0xc00 */ > + uint8_t reserved17[508]; > + uint32_t uddr14; /* 0xe00 */ > + > +} __packed; You don't need this. > + > +#define PXA25X_UDC_BASE 0x40600000 > + > +#define UDCCR_UDE (1 << 0) > +#define UDCCR_UDA (1 << 1) > +#define UDCCR_RSM (1 << 2) > +#define UDCCR_RESIR (1 << 3) > +#define UDCCR_SUSIR (1 << 4) > +#define UDCCR_SRM (1 << 5) > +#define UDCCR_RSTIR (1 << 6) > +#define UDCCR_REM (1 << 7) > + > +/* Bulk IN endpoint 1/6/11 */ > +#define UDCCS_BI_TSP (1 << 7) > +#define UDCCS_BI_FST (1 << 5) > +#define UDCCS_BI_SST (1 << 4) > +#define UDCCS_BI_TUR (1 << 3) > +#define UDCCS_BI_FTF (1 << 2) > +#define UDCCS_BI_TPC (1 << 1) > +#define UDCCS_BI_TFS (1 << 0) > + > +/* Bulk OUT endpoint 2/7/12 */ > +#define UDCCS_BO_RSP (1 << 7) > +#define UDCCS_BO_RNE (1 << 6) > +#define UDCCS_BO_FST (1 << 5) > +#define UDCCS_BO_SST (1 << 4) > +#define UDCCS_BO_DME (1 << 3) > +#define UDCCS_BO_RPC (1 << 1) > +#define UDCCS_BO_RFS (1 << 0) > + > +/* Isochronous OUT endpoint 4/9/14 */ > +#define UDCCS_IO_RSP (1 << 7) > +#define UDCCS_IO_RNE (1 << 6) > +#define UDCCS_IO_DME (1 << 3) > +#define UDCCS_IO_ROF (1 << 2) > +#define UDCCS_IO_RPC (1 << 1) > +#define UDCCS_IO_RFS (1 << 0) > + > +/* Control endpoint 0 */ > +#define UDCCS0_OPR (1 << 0) > +#define UDCCS0_IPR (1 << 1) > +#define UDCCS0_FTF (1 << 2) > +#define UDCCS0_DRWF (1 << 3) > +#define UDCCS0_SST (1 << 4) > +#define UDCCS0_FST (1 << 5) > +#define UDCCS0_RNE (1 << 6) > +#define UDCCS0_SA (1 << 7) > + > +#define UICR0_IM0 (1 << 0) > + > +#define USIR0_IR0 (1 << 0) > +#define USIR0_IR1 (1 << 1) > +#define USIR0_IR2 (1 << 2) > +#define USIR0_IR3 (1 << 3) > +#define USIR0_IR4 (1 << 4) > +#define USIR0_IR5 (1 << 5) > +#define USIR0_IR6 (1 << 6) > +#define USIR0_IR7 (1 << 7) > + > +#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ > +#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ > +/* latest pxa255 errata define new "must be one" bits in UDCCFR */ > +#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) What errata and where? Please document it in the comment. Also, is the register only 8 bit wide? > +#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ > +#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ > +#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ > +#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ > +#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ > + > +#endif /* __REGS_USB_H__ */