* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-23 3:07 ` Mike Frysinger
2012-08-24 0:22 ` Daniel Schwierzeck
2012-08-20 14:22 ` [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files Zhizhou Zhang
` (9 subsequent siblings)
10 siblings, 2 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
These files are derived from arch/mips/cpu/mips32/*. Howerver some
Changes are made:
*.S: changes ABI o32 to n64
config.mk: add mips64 building cflags
cpu.c: add cache size probe
interrupts.c: implement enable_interrupts and disable_interrupts
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/cpu/mips64/Makefile | 47 +++++++
arch/mips/cpu/mips64/config.mk | 39 ++++++
arch/mips/cpu/mips64/cpu.c | 124 ++++++++++++++++++
arch/mips/cpu/mips64/interrupts.c | 39 ++++++
arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/time.c | 86 +++++++++++++
6 files changed, 591 insertions(+)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
new file mode 100644
index 0000000..335fe88
--- /dev/null
+++ b/arch/mips/cpu/mips64/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS-y = cpu.o interrupts.o time.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
new file mode 100644
index 0000000..26f79e6
--- /dev/null
+++ b/arch/mips/cpu/mips64/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+ENDIANNESS = -EL
+
+MIPSFLAGS += $(ENDIANNESS)
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+PLATFORM_LDFLAGS += -m elf64ltsmip
+
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 0000000..348ccfe
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+#include <linux/compiler.h>
+
+void __weak _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, "*** reset failed ***\n");
+ return 0;
+}
+
+static struct cache_desc icache, dcache;
+
+void cache_probe(void)
+{
+ int config, lsize;
+
+ config = read_c0_config1();
+ lsize = (config >> 19) & 7;
+ if (lsize) { /* icache present */
+ icache.linesz = 2 << lsize;
+ icache.sets = 32 << (((config >> 22) + 1) & 7);
+ icache.ways = 1 + ((config >> 16) & 7);
+ icache.size = icache.sets *
+ icache.ways *
+ icache.linesz;
+ }
+
+ lsize = (config >> 10) & 7;
+ if (lsize) { /* dcache present */
+ dcache.linesz = 2 << lsize;
+ dcache.sets = 32 << (((config >> 13) + 1) & 7);
+ dcache.ways = 1 + ((config >> 7) & 7);
+ dcache.size = dcache.sets *
+ dcache.ways *
+ dcache.linesz;
+ }
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long addr, aend;
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ addr = start_addr & ~(icache.linesz - 1);
+ aend = (start_addr + size - 1) & ~(icache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += icache.linesz;
+ }
+
+ addr = start_addr & ~(dcache.linesz - 1);
+ aend = (start_addr + size - 1) & ~(dcache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr & ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr & ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 0000000..f661fb0
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status | ST0_IE);
+}
+
+int disable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status & ~ST0_IE);
+ return status | ST0_IE;
+}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644
index 0000000..b8585e7
--- /dev/null
+++ b/arch/mips/cpu/mips64/start.S
@@ -0,0 +1,256 @@
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ * Copyright (c) 2012 Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+ dla t9, cache_probe
+ jalr t9
+ nop
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ li t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ li t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 0000000..350896a
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return (timestamp - base);
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
@ 2012-08-23 3:07 ` Mike Frysinger
2012-08-23 13:57 ` Zhi-zhou Zhang
2012-08-24 0:22 ` Daniel Schwierzeck
1 sibling, 1 reply; 24+ messages in thread
From: Mike Frysinger @ 2012-08-23 3:07 UTC (permalink / raw)
To: u-boot
On Monday 20 August 2012 10:22:23 Zhizhou Zhang wrote:
> +void __weak _machine_restart(void)
> +{
> +}
this should be:
void __noreturn __weak _machine_restart(void)
{
while (1);
}
there should also be a prototype for this in one of the mips64 headers
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + _machine_restart();
> +
> + fprintf(stderr, "*** reset failed ***\n");
> + return 0;
> +}
then this would be:
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
_machine_restart();
}
-mike
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^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-23 3:07 ` Mike Frysinger
@ 2012-08-23 13:57 ` Zhi-zhou Zhang
0 siblings, 0 replies; 24+ messages in thread
From: Zhi-zhou Zhang @ 2012-08-23 13:57 UTC (permalink / raw)
To: u-boot
On Thu, Aug 23, 2012 at 11:07 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Monday 20 August 2012 10:22:23 Zhizhou Zhang wrote:
> > +void __weak _machine_restart(void)
> > +{
> > +}
>
> this should be:
> void __noreturn __weak _machine_restart(void)
> {
> while (1);
> }
>
> there should also be a prototype for this in one of the mips64 headers
>
> > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> > +{
> > + _machine_restart();
> > +
> > + fprintf(stderr, "*** reset failed ***\n");
> > + return 0;
> > +}
>
> then this would be:
> int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> _machine_restart();
> }
> -mike
>
Yes, you are right. thanks
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
2012-08-23 3:07 ` Mike Frysinger
@ 2012-08-24 0:22 ` Daniel Schwierzeck
2012-08-26 3:10 ` Zhi-zhou Zhang
2012-08-26 12:12 ` Zhi-zhou Zhang
1 sibling, 2 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-24 0:22 UTC (permalink / raw)
To: u-boot
2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> These files are derived from arch/mips/cpu/mips32/*. Howerver some
> Changes are made:
> *.S: changes ABI o32 to n64
> config.mk: add mips64 building cflags
> cpu.c: add cache size probe
> interrupts.c: implement enable_interrupts and disable_interrupts
>
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> arch/mips/cpu/mips64/Makefile | 47 +++++++
> arch/mips/cpu/mips64/config.mk | 39 ++++++
> arch/mips/cpu/mips64/cpu.c | 124 ++++++++++++++++++
> arch/mips/cpu/mips64/interrupts.c | 39 ++++++
> arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
> arch/mips/cpu/mips64/time.c | 86 +++++++++++++
> 6 files changed, 591 insertions(+)
> create mode 100644 arch/mips/cpu/mips64/Makefile
> create mode 100644 arch/mips/cpu/mips64/config.mk
> create mode 100644 arch/mips/cpu/mips64/cpu.c
> create mode 100644 arch/mips/cpu/mips64/interrupts.c
> create mode 100644 arch/mips/cpu/mips64/start.S
> create mode 100644 arch/mips/cpu/mips64/time.c
>
> diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
> new file mode 100644
> index 0000000..335fe88
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/Makefile
> @@ -0,0 +1,47 @@
> +#
> +# (C) Copyright 2003-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(CPU).o
> +
> +START = start.o
> +COBJS-y = cpu.o interrupts.o time.o
> +
> +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
> +START := $(addprefix $(obj),$(START))
> +
> +all: $(obj).depend $(START) $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
> new file mode 100644
> index 0000000..26f79e6
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/config.mk
> @@ -0,0 +1,39 @@
> +#
> +# (C) Copyright 2003
> +# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +#
> +# Default optimization level for MIPS64
> +#
> +# Note: Toolchains with binutils prior to v2.16
> +# are no longer supported by U-Boot MIPS tree!
> +#
> +MIPSFLAGS = -march=mips64
> +
> +ENDIANNESS = -EL
> +
> +MIPSFLAGS += $(ENDIANNESS)
with current master branch in git://git.denx.de/u-boot-mips.git you can drop the
endianess flags which are now handled in arch/mips/config.mk
> +
> +PLATFORM_CPPFLAGS += $(MIPSFLAGS)
> +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
> +PLATFORM_LDFLAGS += -m elf64ltsmip
> +
> diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
> new file mode 100644
> index 0000000..348ccfe
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/cpu.c
> @@ -0,0 +1,124 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> + * Zhi-zhou Zhang <etou.zh@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <netdev.h>
> +#include <asm/mipsregs.h>
> +#include <asm/cacheops.h>
> +#include <asm/reboot.h>
> +#include <linux/compiler.h>
> +
> +void __weak _machine_restart(void)
> +{
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + _machine_restart();
> +
> + fprintf(stderr, "*** reset failed ***\n");
> + return 0;
> +}
> +
> +static struct cache_desc icache, dcache;
> +
> +void cache_probe(void)
> +{
> + int config, lsize;
> +
> + config = read_c0_config1();
> + lsize = (config >> 19) & 7;
> + if (lsize) { /* icache present */
> + icache.linesz = 2 << lsize;
> + icache.sets = 32 << (((config >> 22) + 1) & 7);
> + icache.ways = 1 + ((config >> 16) & 7);
> + icache.size = icache.sets *
> + icache.ways *
> + icache.linesz;
> + }
> +
> + lsize = (config >> 10) & 7;
> + if (lsize) { /* dcache present */
> + dcache.linesz = 2 << lsize;
> + dcache.sets = 32 << (((config >> 13) + 1) & 7);
> + dcache.ways = 1 + ((config >> 7) & 7);
> + dcache.size = dcache.sets *
> + dcache.ways *
> + dcache.linesz;
> + }
> +}
> +
> +void flush_cache(ulong start_addr, ulong size)
> +{
> + unsigned long addr, aend;
> +
> + /* aend will be miscalculated when size is zero, so we return here */
> + if (size == 0)
> + return;
> +
> + addr = start_addr & ~(icache.linesz - 1);
> + aend = (start_addr + size - 1) & ~(icache.linesz - 1);
> + while (1) {
> + cache_op(Hit_Invalidate_I, addr);
> + if (addr == aend)
> + break;
> + addr += icache.linesz;
> + }
> +
> + addr = start_addr & ~(dcache.linesz - 1);
> + aend = (start_addr + size - 1) & ~(dcache.linesz - 1);
> + while (1) {
> + cache_op(Hit_Writeback_Inv_D, addr);
> + if (addr == aend)
> + break;
> + addr += dcache.linesz;
> + }
> +}
> +
> +void flush_dcache_range(ulong start_addr, ulong stop)
> +{
> + unsigned long addr = start_addr & ~(dcache.linesz - 1);
> + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
> +
> + while (1) {
> + cache_op(Hit_Writeback_Inv_D, addr);
> + if (addr == aend)
> + break;
> + addr += dcache.linesz;
> + }
> +}
> +
> +void invalidate_dcache_range(ulong start_addr, ulong stop)
> +{
> + unsigned long addr = start_addr & ~(dcache.linesz - 1);
> + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
> +
> + while (1) {
> + cache_op(Hit_Invalidate_D, addr);
> + if (addr == aend)
> + break;
> + addr += dcache.linesz;
> + }
> +}
> diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
> new file mode 100644
> index 0000000..f661fb0
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/interrupts.c
> @@ -0,0 +1,39 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> + * Zhi-zhou Zhang <etou.zh@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mipsregs.h>
> +
> +void enable_interrupts(void)
> +{
> + int status = read_c0_status();
> + write_c0_status(status | ST0_IE);
> +}
> +
> +int disable_interrupts(void)
> +{
> + int status = read_c0_status();
> + write_c0_status(status & ~ST0_IE);
> + return status | ST0_IE;
> +}
currently we cannot use interrupts or setup any interrupt handlers in
u-boot-mips.
Please leave those functions empty.
> diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
> new file mode 100644
> index 0000000..b8585e7
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/start.S
> @@ -0,0 +1,256 @@
> +/*
> + * Startup Code for MIPS64 CPU-core
> + *
> + * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
> + * Copyright (c) 2012 Zhi-zhou Zhang <etou.zh@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any dlater version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +
> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> +#endif
> +
> + /*
> + * For the moment disable interrupts, mark the kernel mode and
> + * set ST0_KX so that the CPU does not spit fire when using
> + * 64-bit addresses.
> + */
> + .macro setup_c0_status set clr
> + .set push
> + mfc0 t0, CP0_STATUS
> + or t0, ST0_CU0 | \set | 0x1f | \clr
> + xor t0, 0x1f | \clr
> + mtc0 t0, CP0_STATUS
> + .set noreorder
> + sll zero, 3 # ehb
> + .set pop
> + .endm
> +
> + .set noreorder
> +
> + .globl _start
> + .text
> +_start:
> + .org 0x000
> + b reset
> + nop
> + .org 0x080
> + b romReserved
> + nop
> + .org 0x100
> + b romReserved
> + nop
> + .org 0x180
> + b romReserved
> + nop
> + .org 0x200
> + b romReserved
> + nop
> + .org 0x280
> + b romReserved
> + nop
> + .org 0x300
> + b romReserved
> + nop
> + .org 0x380
> + b romReserved
> + nop
> + .org 0x480
> + b romReserved
> + nop
> +
> + /*
> + * We hope there are no more reserved vectors!
> + * 128 * 8 == 1024 == 0x400
> + * so this is address R_VEC+0x400 == 0xbfc00400
> + */
> + .org 0x500
> + .align 4
> +reset:
> +
> + /* Clear watch registers */
> + dmtc0 zero, CP0_WATCHLO
> + dmtc0 zero, CP0_WATCHHI
> +
> + /* WP(Watch Pending), SW0/1 should be cleared */
> + mtc0 zero, CP0_CAUSE
> +
> + setup_c0_status ST0_KX 0
> +
> + /* Init Timer */
> + mtc0 zero, CP0_COUNT
> + mtc0 zero, CP0_COMPARE
> +
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> + /* CONFIG0 register */
> + li t0, CONF_CM_UNCACHED
> + mtc0 t0, CP0_CONFIG
> +#endif
> +
> + /* Initialize $gp */
> + bal 1f
> + nop
> + .dword _gp
> +1:
> + ld gp, 0(ra)
> +
> + dla t9, cache_probe
> + jalr t9
> + nop
calling a C function is not supposed to work here because no stack
pointer has been setup yet.
I checked with Sourcery 2011.09 and 2012.03. The stack is always
utilized in cache_probe.
Either you rewrite the cache_probe function in assembler or you use
the existing config options
and you could drop the cache probing.
> +
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> + /* Initialize any external memory */
> + dla t9, lowlevel_init
> + jalr t9
> + nop
> +
> + /* ... and enable them */
> + li t0, CONFIG_SYS_MIPS_CACHE_MODE
> + mtc0 t0, CP0_CONFIG
> +#endif
> +
> + /* Set up temporary stack */
> + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
> + dla sp, 0(t0)
> +
> + dla t9, board_init_f
> + jr t9
> + nop
> +
> +/*
> + * void relocate_code (addr_sp, gd, addr_moni)
> + *
> + * This "function" does not return, instead it continues in RAM
> + * after relocating the monitor code.
> + *
> + * a0 = addr_sp
> + * a1 = gd
> + * a2 = destination address
> + */
> + .globl relocate_code
> + .ent relocate_code
> +relocate_code:
> + move sp, a0 # set new stack pointer
> +
> + li t0, CONFIG_SYS_MONITOR_BASE
> + dla t3, in_ram
> + ld t2, -24(t3) # t2 <-- uboot_end_data
> + move t1, a2
> + move s2, a2 # s2 <-- destination address
> +
> + /*
> + * Fix $gp:
> + *
> + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
> + */
> + move t8, gp
> + dsub gp, CONFIG_SYS_MONITOR_BASE
> + dadd gp, a2 # gp now adjusted
> + dsub s1, gp, t8 # s1 <-- relocation offset
> +
> + /*
> + * t0 = source address
> + * t1 = target address
> + * t2 = source end address
> + */
> +
> + /*
> + * Save destination address and size for dlater usage in flush_cache()
> + */
> + move s0, a1 # save gd in s0
> + move a0, t1 # a0 <-- destination addr
> + dsub a1, t2, t0 # a1 <-- size
> +
> +1:
> + lw t3, 0(t0)
> + sw t3, 0(t1)
> + daddu t0, 4
> + ble t0, t2, 1b
> + daddu t1, 4
> +
> + /* If caches were enabled, we would have to flush them here. */
> +
> + /* a0 & a1 are already set up for flush_cache(start, size) */
> + dla t9, flush_cache
> + jalr t9
> + nop
> +
> + /* Jump to where we've relocated ourselves */
> + daddi t0, s2, in_ram - _start
> + jr t0
> + nop
> +
> + .dword _gp
> + .dword _GLOBAL_OFFSET_TABLE_
> + .dword uboot_end_data
> + .dword uboot_end
> + .dword num_got_entries
> +
> +in_ram:
> + /*
> + * Now we want to update GOT.
> + *
> + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
> + * generated by GNU ld. Skip these reserved entries from relocation.
> + */
> + ld t3, -8(t0) # t3 <-- num_got_entries
> + ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
> + ld t9, -40(t0) # t9 <-- _gp
> + dsub t8, t9 # compute offset
> + dadd t8, t8, gp # t8 now holds relocated _G_O_T_
> + daddi t8, t8, 16 # skipping first two entries
> + li t2, 2
> +1:
> + ld t1, 0(t8)
> + beqz t1, 2f
> + dadd t1, s1
> + sd t1, 0(t8)
> +2:
> + daddi t2, 1
> + blt t2, t3, 1b
> + daddi t8, 8
> +
> + /* Clear BSS */
> + ld t1, -24(t0) # t1 <-- uboot_end_data
> + ld t2, -16(t0) # t2 <-- uboot_end
> + dadd t1, s1 # adjust pointers
> + dadd t2, s1
> +
> + dsub t1, 8
> +1:
> + daddi t1, 8
> + bltl t1, t2, 1b
> + sd zero, 0(t1)
> +
> + move a0, s0 # a0 <-- gd
> + dla t9, board_init_r
> + jr t9
> + move a1, s2
> +
> + .end relocate_code
> +
> + /* Exception handlers */
> +romReserved:
> + b romReserved
> diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
> new file mode 100644
> index 0000000..350896a
> --- /dev/null
> +++ b/arch/mips/cpu/mips64/time.c
> @@ -0,0 +1,86 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mipsregs.h>
> +
> +static unsigned long timestamp;
> +
> +/* how many counter cycles in a jiffy */
> +#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
> +
> +/*
> + * timer without interrupts
> + */
> +
> +int timer_init(void)
> +{
> + /* Set up the timer for the first expiration. */
> + timestamp = 0;
> + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
> +
> + return 0;
> +}
> +
> +ulong get_timer(ulong base)
> +{
> + unsigned int count;
> + unsigned int expirelo = read_c0_compare();
> +
> + /* Check to see if we have missed any timestamps. */
> + count = read_c0_count();
> + while ((count - expirelo) < 0x7fffffff) {
> + expirelo += CYCLES_PER_JIFFY;
> + timestamp++;
> + }
> + write_c0_compare(expirelo);
> +
> + return (timestamp - base);
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> + unsigned int tmo;
> +
> + tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
> + while ((tmo - read_c0_count()) < 0x7fffffff)
> + /*NOP*/;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long long).
> + * On MIPS it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> + return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On MIPS it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> + return CONFIG_SYS_HZ;
> +}
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-24 0:22 ` Daniel Schwierzeck
@ 2012-08-26 3:10 ` Zhi-zhou Zhang
2012-08-26 12:12 ` Zhi-zhou Zhang
1 sibling, 0 replies; 24+ messages in thread
From: Zhi-zhou Zhang @ 2012-08-26 3:10 UTC (permalink / raw)
To: u-boot
On Fri, Aug 24, 2012 at 8:22 AM, Daniel Schwierzeck <
daniel.schwierzeck@gmail.com> wrote:
> 2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> > These files are derived from arch/mips/cpu/mips32/*. Howerver some
> > Changes are made:
> > *.S: changes ABI o32 to n64
> > config.mk: add mips64 building cflags
> > cpu.c: add cache size probe
> > interrupts.c: implement enable_interrupts and disable_interrupts
> >
> > Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> > ---
> > arch/mips/cpu/mips64/Makefile | 47 +++++++
> > arch/mips/cpu/mips64/config.mk | 39 ++++++
> > arch/mips/cpu/mips64/cpu.c | 124 ++++++++++++++++++
> > arch/mips/cpu/mips64/interrupts.c | 39 ++++++
> > arch/mips/cpu/mips64/start.S | 256
> +++++++++++++++++++++++++++++++++++++
> > arch/mips/cpu/mips64/time.c | 86 +++++++++++++
> > 6 files changed, 591 insertions(+)
> > create mode 100644 arch/mips/cpu/mips64/Makefile
> > create mode 100644 arch/mips/cpu/mips64/config.mk
> > create mode 100644 arch/mips/cpu/mips64/cpu.c
> > create mode 100644 arch/mips/cpu/mips64/interrupts.c
> > create mode 100644 arch/mips/cpu/mips64/start.S
> > create mode 100644 arch/mips/cpu/mips64/time.c
> >
> > diff --git a/arch/mips/cpu/mips64/Makefile
> b/arch/mips/cpu/mips64/Makefile
> > new file mode 100644
> > index 0000000..335fe88
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/Makefile
> > @@ -0,0 +1,47 @@
> > +#
> > +# (C) Copyright 2003-2006
> > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > +#
> > +# See file CREDITS for list of people who contributed to this
> > +# project.
> > +#
> > +# This program is free software; you can redistribute it and/or
> > +# modify it under the terms of the GNU General Public License as
> > +# published by the Free Software Foundation; either version 2 of
> > +# the License, or (at your option) any later version.
> > +#
> > +# This program is distributed in the hope that it will be useful,
> > +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > +# GNU General Public License for more details.
> > +#
> > +# You should have received a copy of the GNU General Public License
> > +# along with this program; if not, write to the Free Software
> > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > +# MA 02111-1307 USA
> > +#
> > +
> > +include $(TOPDIR)/config.mk
> > +
> > +LIB = $(obj)lib$(CPU).o
> > +
> > +START = start.o
> > +COBJS-y = cpu.o interrupts.o time.o
> > +
> > +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> > +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
> > +START := $(addprefix $(obj),$(START))
> > +
> > +all: $(obj).depend $(START) $(LIB)
> > +
> > +$(LIB): $(OBJS)
> > + $(call cmd_link_o_target, $(OBJS))
> > +
> >
> +#########################################################################
> > +
> > +# defines $(obj).depend target
> > +include $(SRCTREE)/rules.mk
> > +
> > +sinclude $(obj).depend
> > +
> >
> +#########################################################################
> > diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/
> config.mk
> > new file mode 100644
> > index 0000000..26f79e6
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/config.mk
> > @@ -0,0 +1,39 @@
> > +#
> > +# (C) Copyright 2003
> > +# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> > +#
> > +# See file CREDITS for list of people who contributed to this
> > +# project.
> > +#
> > +# This program is free software; you can redistribute it and/or
> > +# modify it under the terms of the GNU General Public License as
> > +# published by the Free Software Foundation; either version 2 of
> > +# the License, or (at your option) any later version.
> > +#
> > +# This program is distributed in the hope that it will be useful,
> > +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > +# GNU General Public License for more details.
> > +#
> > +# You should have received a copy of the GNU General Public License
> > +# along with this program; if not, write to the Free Software
> > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > +# MA 02111-1307 USA
> > +#
> > +
> > +#
> > +# Default optimization level for MIPS64
> > +#
> > +# Note: Toolchains with binutils prior to v2.16
> > +# are no longer supported by U-Boot MIPS tree!
> > +#
> > +MIPSFLAGS = -march=mips64
> > +
> > +ENDIANNESS = -EL
> > +
> > +MIPSFLAGS += $(ENDIANNESS)
>
> with current master branch in git://git.denx.de/u-boot-mips.git you can
> drop the
> endianess flags which are now handled in arch/mips/config.mk
>
> > +
> > +PLATFORM_CPPFLAGS += $(MIPSFLAGS)
> > +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
> > +PLATFORM_LDFLAGS += -m elf64ltsmip
> > +
> > diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
> > new file mode 100644
> > index 0000000..348ccfe
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/cpu.c
> > @@ -0,0 +1,124 @@
> > +/*
> > + * (C) Copyright 2003
> > + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> > + * Zhi-zhou Zhang <etou.zh@gmail.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <command.h>
> > +#include <netdev.h>
> > +#include <asm/mipsregs.h>
> > +#include <asm/cacheops.h>
> > +#include <asm/reboot.h>
> > +#include <linux/compiler.h>
> > +
> > +void __weak _machine_restart(void)
> > +{
> > +}
> > +
> > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> > +{
> > + _machine_restart();
> > +
> > + fprintf(stderr, "*** reset failed ***\n");
> > + return 0;
> > +}
> > +
> > +static struct cache_desc icache, dcache;
> > +
> > +void cache_probe(void)
> > +{
> > + int config, lsize;
> > +
> > + config = read_c0_config1();
> > + lsize = (config >> 19) & 7;
> > + if (lsize) { /* icache present */
> > + icache.linesz = 2 << lsize;
> > + icache.sets = 32 << (((config >> 22) + 1) & 7);
> > + icache.ways = 1 + ((config >> 16) & 7);
> > + icache.size = icache.sets *
> > + icache.ways *
> > + icache.linesz;
> > + }
> > +
> > + lsize = (config >> 10) & 7;
> > + if (lsize) { /* dcache present */
> > + dcache.linesz = 2 << lsize;
> > + dcache.sets = 32 << (((config >> 13) + 1) & 7);
> > + dcache.ways = 1 + ((config >> 7) & 7);
> > + dcache.size = dcache.sets *
> > + dcache.ways *
> > + dcache.linesz;
> > + }
> > +}
> > +
> > +void flush_cache(ulong start_addr, ulong size)
> > +{
> > + unsigned long addr, aend;
> > +
> > + /* aend will be miscalculated when size is zero, so we return
> here */
> > + if (size == 0)
> > + return;
> > +
> > + addr = start_addr & ~(icache.linesz - 1);
> > + aend = (start_addr + size - 1) & ~(icache.linesz - 1);
> > + while (1) {
> > + cache_op(Hit_Invalidate_I, addr);
> > + if (addr == aend)
> > + break;
> > + addr += icache.linesz;
> > + }
> > +
> > + addr = start_addr & ~(dcache.linesz - 1);
> > + aend = (start_addr + size - 1) & ~(dcache.linesz - 1);
> > + while (1) {
> > + cache_op(Hit_Writeback_Inv_D, addr);
> > + if (addr == aend)
> > + break;
> > + addr += dcache.linesz;
> > + }
> > +}
> > +
> > +void flush_dcache_range(ulong start_addr, ulong stop)
> > +{
> > + unsigned long addr = start_addr & ~(dcache.linesz - 1);
> > + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
> > +
> > + while (1) {
> > + cache_op(Hit_Writeback_Inv_D, addr);
> > + if (addr == aend)
> > + break;
> > + addr += dcache.linesz;
> > + }
> > +}
> > +
> > +void invalidate_dcache_range(ulong start_addr, ulong stop)
> > +{
> > + unsigned long addr = start_addr & ~(dcache.linesz - 1);
> > + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
> > +
> > + while (1) {
> > + cache_op(Hit_Invalidate_D, addr);
> > + if (addr == aend)
> > + break;
> > + addr += dcache.linesz;
> > + }
> > +}
> > diff --git a/arch/mips/cpu/mips64/interrupts.c
> b/arch/mips/cpu/mips64/interrupts.c
> > new file mode 100644
> > index 0000000..f661fb0
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/interrupts.c
> > @@ -0,0 +1,39 @@
> > +/*
> > + * (C) Copyright 2003
> > + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
> > + * Zhi-zhou Zhang <etou.zh@gmail.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/mipsregs.h>
> > +
> > +void enable_interrupts(void)
> > +{
> > + int status = read_c0_status();
> > + write_c0_status(status | ST0_IE);
> > +}
> > +
> > +int disable_interrupts(void)
> > +{
> > + int status = read_c0_status();
> > + write_c0_status(status & ~ST0_IE);
> > + return status | ST0_IE;
> > +}
>
> currently we cannot use interrupts or setup any interrupt handlers in
> u-boot-mips.
> Please leave those functions empty.
>
> > diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
> > new file mode 100644
> > index 0000000..b8585e7
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/start.S
> > @@ -0,0 +1,256 @@
> > +/*
> > + * Startup Code for MIPS64 CPU-core
> > + *
> > + * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
> > + * Copyright (c) 2012 Zhi-zhou Zhang <etou.zh@gmail.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any dlater version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <asm-offsets.h>
> > +#include <config.h>
> > +#include <asm/regdef.h>
> > +#include <asm/mipsregs.h>
> > +
> > +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
> > +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> > +#endif
> > +
> > + /*
> > + * For the moment disable interrupts, mark the kernel mode and
> > + * set ST0_KX so that the CPU does not spit fire when using
> > + * 64-bit addresses.
> > + */
> > + .macro setup_c0_status set clr
> > + .set push
> > + mfc0 t0, CP0_STATUS
> > + or t0, ST0_CU0 | \set | 0x1f | \clr
> > + xor t0, 0x1f | \clr
> > + mtc0 t0, CP0_STATUS
> > + .set noreorder
> > + sll zero, 3 # ehb
> > + .set pop
> > + .endm
> > +
> > + .set noreorder
> > +
> > + .globl _start
> > + .text
> > +_start:
> > + .org 0x000
> > + b reset
> > + nop
> > + .org 0x080
> > + b romReserved
> > + nop
> > + .org 0x100
> > + b romReserved
> > + nop
> > + .org 0x180
> > + b romReserved
> > + nop
> > + .org 0x200
> > + b romReserved
> > + nop
> > + .org 0x280
> > + b romReserved
> > + nop
> > + .org 0x300
> > + b romReserved
> > + nop
> > + .org 0x380
> > + b romReserved
> > + nop
> > + .org 0x480
> > + b romReserved
> > + nop
> > +
> > + /*
> > + * We hope there are no more reserved vectors!
> > + * 128 * 8 == 1024 == 0x400
> > + * so this is address R_VEC+0x400 == 0xbfc00400
> > + */
> > + .org 0x500
> > + .align 4
> > +reset:
> > +
> > + /* Clear watch registers */
> > + dmtc0 zero, CP0_WATCHLO
> > + dmtc0 zero, CP0_WATCHHI
> > +
> > + /* WP(Watch Pending), SW0/1 should be cleared */
> > + mtc0 zero, CP0_CAUSE
> > +
> > + setup_c0_status ST0_KX 0
> > +
> > + /* Init Timer */
> > + mtc0 zero, CP0_COUNT
> > + mtc0 zero, CP0_COMPARE
> > +
> > +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> > + /* CONFIG0 register */
> > + li t0, CONF_CM_UNCACHED
> > + mtc0 t0, CP0_CONFIG
> > +#endif
> > +
> > + /* Initialize $gp */
> > + bal 1f
> > + nop
> > + .dword _gp
> > +1:
> > + ld gp, 0(ra)
> > +
> > + dla t9, cache_probe
> > + jalr t9
> > + nop
>
> calling a C function is not supposed to work here because no stack
> pointer has been setup yet.
> I checked with Sourcery 2011.09 and 2012.03. The stack is always
> utilized in cache_probe.
> Either you rewrite the cache_probe function in assembler or you use
> the existing config options
> and you could drop the cache probing.
>
> Thanks,
So could I put it in board/qemu-mips/qemu-mips.c? I think when power on,
all cache are in invalid state, we don't need flush it at all. So only if
we do cache_probe before calling flush opertaions, everything goes ok. am i
right?
> > +
> > +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> > + /* Initialize any external memory */
> > + dla t9, lowlevel_init
> > + jalr t9
> > + nop
> > +
> > + /* ... and enable them */
> > + li t0, CONFIG_SYS_MIPS_CACHE_MODE
> > + mtc0 t0, CP0_CONFIG
> > +#endif
> > +
> > + /* Set up temporary stack */
> > + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
> > + dla sp, 0(t0)
> > +
> > + dla t9, board_init_f
> > + jr t9
> > + nop
> > +
> > +/*
> > + * void relocate_code (addr_sp, gd, addr_moni)
> > + *
> > + * This "function" does not return, instead it continues in RAM
> > + * after relocating the monitor code.
> > + *
> > + * a0 = addr_sp
> > + * a1 = gd
> > + * a2 = destination address
> > + */
> > + .globl relocate_code
> > + .ent relocate_code
> > +relocate_code:
> > + move sp, a0 # set new stack pointer
> > +
> > + li t0, CONFIG_SYS_MONITOR_BASE
> > + dla t3, in_ram
> > + ld t2, -24(t3) # t2 <-- uboot_end_data
> > + move t1, a2
> > + move s2, a2 # s2 <-- destination address
> > +
> > + /*
> > + * Fix $gp:
> > + *
> > + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination
> Address
> > + */
> > + move t8, gp
> > + dsub gp, CONFIG_SYS_MONITOR_BASE
> > + dadd gp, a2 # gp now adjusted
> > + dsub s1, gp, t8 # s1 <-- relocation offset
> > +
> > + /*
> > + * t0 = source address
> > + * t1 = target address
> > + * t2 = source end address
> > + */
> > +
> > + /*
> > + * Save destination address and size for dlater usage in
> flush_cache()
> > + */
> > + move s0, a1 # save gd in s0
> > + move a0, t1 # a0 <-- destination addr
> > + dsub a1, t2, t0 # a1 <-- size
> > +
> > +1:
> > + lw t3, 0(t0)
> > + sw t3, 0(t1)
> > + daddu t0, 4
> > + ble t0, t2, 1b
> > + daddu t1, 4
> > +
> > + /* If caches were enabled, we would have to flush them here. */
> > +
> > + /* a0 & a1 are already set up for flush_cache(start, size) */
> > + dla t9, flush_cache
> > + jalr t9
> > + nop
> > +
> > + /* Jump to where we've relocated ourselves */
> > + daddi t0, s2, in_ram - _start
> > + jr t0
> > + nop
> > +
> > + .dword _gp
> > + .dword _GLOBAL_OFFSET_TABLE_
> > + .dword uboot_end_data
> > + .dword uboot_end
> > + .dword num_got_entries
> > +
> > +in_ram:
> > + /*
> > + * Now we want to update GOT.
> > + *
> > + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic
> object
> > + * generated by GNU ld. Skip these reserved entries from
> relocation.
> > + */
> > + ld t3, -8(t0) # t3 <-- num_got_entries
> > + ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
> > + ld t9, -40(t0) # t9 <-- _gp
> > + dsub t8, t9 # compute offset
> > + dadd t8, t8, gp # t8 now holds relocated _G_O_T_
> > + daddi t8, t8, 16 # skipping first two entries
> > + li t2, 2
> > +1:
> > + ld t1, 0(t8)
> > + beqz t1, 2f
> > + dadd t1, s1
> > + sd t1, 0(t8)
> > +2:
> > + daddi t2, 1
> > + blt t2, t3, 1b
> > + daddi t8, 8
> > +
> > + /* Clear BSS */
> > + ld t1, -24(t0) # t1 <-- uboot_end_data
> > + ld t2, -16(t0) # t2 <-- uboot_end
> > + dadd t1, s1 # adjust pointers
> > + dadd t2, s1
> > +
> > + dsub t1, 8
> > +1:
> > + daddi t1, 8
> > + bltl t1, t2, 1b
> > + sd zero, 0(t1)
> > +
> > + move a0, s0 # a0 <-- gd
> > + dla t9, board_init_r
> > + jr t9
> > + move a1, s2
> > +
> > + .end relocate_code
> > +
> > + /* Exception handlers */
> > +romReserved:
> > + b romReserved
> > diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
> > new file mode 100644
> > index 0000000..350896a
> > --- /dev/null
> > +++ b/arch/mips/cpu/mips64/time.c
> > @@ -0,0 +1,86 @@
> > +/*
> > + * (C) Copyright 2003
> > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/mipsregs.h>
> > +
> > +static unsigned long timestamp;
> > +
> > +/* how many counter cycles in a jiffy */
> > +#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ +
> CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
> > +
> > +/*
> > + * timer without interrupts
> > + */
> > +
> > +int timer_init(void)
> > +{
> > + /* Set up the timer for the first expiration. */
> > + timestamp = 0;
> > + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
> > +
> > + return 0;
> > +}
> > +
> > +ulong get_timer(ulong base)
> > +{
> > + unsigned int count;
> > + unsigned int expirelo = read_c0_compare();
> > +
> > + /* Check to see if we have missed any timestamps. */
> > + count = read_c0_count();
> > + while ((count - expirelo) < 0x7fffffff) {
> > + expirelo += CYCLES_PER_JIFFY;
> > + timestamp++;
> > + }
> > + write_c0_compare(expirelo);
> > +
> > + return (timestamp - base);
> > +}
> > +
> > +void __udelay(unsigned long usec)
> > +{
> > + unsigned int tmo;
> > +
> > + tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ /
> 1000000));
> > + while ((tmo - read_c0_count()) < 0x7fffffff)
> > + /*NOP*/;
> > +}
> > +
> > +/*
> > + * This function is derived from PowerPC code (read timebase as long
> long).
> > + * On MIPS it just returns the timer value.
> > + */
> > +unsigned long long get_ticks(void)
> > +{
> > + return get_timer(0);
> > +}
> > +
> > +/*
> > + * This function is derived from PowerPC code (timebase clock
> frequency).
> > + * On MIPS it returns the number of timer ticks per second.
> > + */
> > +ulong get_tbclk(void)
> > +{
> > + return CONFIG_SYS_HZ;
> > +}
> > --
> > 1.7.9.5
> >
>
>
>
> --
> Best regards,
> Daniel
>
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-24 0:22 ` Daniel Schwierzeck
2012-08-26 3:10 ` Zhi-zhou Zhang
@ 2012-08-26 12:12 ` Zhi-zhou Zhang
2012-08-26 14:23 ` Daniel Schwierzeck
1 sibling, 1 reply; 24+ messages in thread
From: Zhi-zhou Zhang @ 2012-08-26 12:12 UTC (permalink / raw)
To: u-boot
>
>
> with current master branch in git://git.denx.de/u-boot-mips.git you can
> drop the
> endianess flags which are now handled in arch/mips/config.mk
>
> Ok, I have done what you ask for. But I didn't find where does
CONFIG_SYS_LITTLE_ENDIAN or CONFIG_SYS_BIG_ENDIAN define.
Could you tell where should I put them?
It seem that putting it in qemu-mips64.h doesn't affect building flags.
>
> currently we cannot use interrupts or setup any interrupt handlers in
> u-boot-mips.
> Please leave those functions empty.
>
>
> calling a C function is not supposed to work here because no stack
> pointer has been setup yet.
> I checked with Sourcery 2011.09 and 2012.03. The stack is always
> utilized in cache_probe.
> Either you rewrite the cache_probe function in assembler or you use
> the existing config options
> and you could drop the cache probing.
>
> I'm afraid I don't say clearly just now. I mean could I call cache_probe
in checkboard()?
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-26 12:12 ` Zhi-zhou Zhang
@ 2012-08-26 14:23 ` Daniel Schwierzeck
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-26 14:23 UTC (permalink / raw)
To: u-boot
2012/8/26 Zhi-zhou Zhang <etou.zh@gmail.com>:
>>
>> with current master branch in git://git.denx.de/u-boot-mips.git you can
>> drop the
>> endianess flags which are now handled in arch/mips/config.mk
>>
> Ok, I have done what you ask for. But I didn't find where does
> CONFIG_SYS_LITTLE_ENDIAN or CONFIG_SYS_BIG_ENDIAN define.
> Could you tell where should I put them?
> It seem that putting it in qemu-mips64.h doesn't affect building flags.
have a look at commit
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=748fd4a621a870d378e4e4f54df76a38fd5d3cba
CONFIG_SYS_LITTLE_ENDIAN or CONFIG_SYS_BIG_ENDIAN could be set in the
board config header file
or in boards.cfg. Usually the header file should be preferred. But for
qemu we want to use the same header file
for both endianess types. Thus we can use the possibilty to put config
options in boards.cfg like I did in my commit.
Adding these lines to boards.cfg should work:
qemu_mips64 mips mips64 qemu-mips
- - qemu-mips64:SYS_BIG_ENDIAN
qemu_mips64el mips mips64 qemu-mips
- - qemu-mips64:SYS_LITTLE_ENDIAN
>>
>>
>> currently we cannot use interrupts or setup any interrupt handlers in
>> u-boot-mips.
>> Please leave those functions empty.
>>
>
>>
>> calling a C function is not supposed to work here because no stack
>>
>> pointer has been setup yet.
>> I checked with Sourcery 2011.09 and 2012.03. The stack is always
>> utilized in cache_probe.
>> Either you rewrite the cache_probe function in assembler or you use
>> the existing config options
>> and you could drop the cache probing.
>>
> I'm afraid I don't say clearly just now. I mean could I call cache_probe in
> checkboard()?
no that is too late. The functions called by mips_cache_reset need to
know the cache sizes.
Currently we are configuring that with the options
CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_ICACHE_SIZE and
CONFIG_SYS_CACHELINE_SIZE. I suggest you do the same for MIPS64.
We can add a runtime cache probing later. But this has to be done in
assembler code. I already have this on my todo list.
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-24 0:22 ` Daniel Schwierzeck
2012-08-20 14:22 ` [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs Zhizhou Zhang
` (8 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
The most important difference between mips32 and mips64 is the address
space. changes in addrspace.h and io.h are for this sake. And this patch
add cache discribe struct in cache.h, and make compatible to mips64 of
some types in posix_types.h.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/include/asm/addrspace.h | 2 +-
arch/mips/include/asm/cache.h | 21 +++++++++++++++++++++
arch/mips/include/asm/io.h | 18 +++++++++++++++++-
arch/mips/include/asm/posix_types.h | 12 +++++++++---
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..e41b9b4 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,25 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets; /* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips64\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 879aae2..0da1dde 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
+#ifndef CONFIG_MIPS64
+ typedef unsigned int __kernel_size_t;
+ typedef int __kernel_ssize_t;
+ typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files
2012-08-20 14:22 ` [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files Zhizhou Zhang
@ 2012-08-24 0:22 ` Daniel Schwierzeck
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-24 0:22 UTC (permalink / raw)
To: u-boot
2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> The most important difference between mips32 and mips64 is the address
> space. changes in addrspace.h and io.h are for this sake. And this patch
> add cache discribe struct in cache.h, and make compatible to mips64 of
> some types in posix_types.h.
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
add a blank line between commit message and SoB tag
> ---
> arch/mips/include/asm/addrspace.h | 2 +-
> arch/mips/include/asm/cache.h | 21 +++++++++++++++++++++
> arch/mips/include/asm/io.h | 18 +++++++++++++++++-
> arch/mips/include/asm/posix_types.h | 12 +++++++++---
> 4 files changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
> index 3a1e6d6..b768bb5 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -136,7 +136,7 @@
> cannot access physical memory directly from core */
> #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
> #else /* !CONFIG_SOC_AU1X00 */
> -#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
> +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
> #endif /* CONFIG_SOC_AU1X00 */
> #endif /* __ASSEMBLY__ */
>
> diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
> index 5406d5d..e41b9b4 100644
> --- a/arch/mips/include/asm/cache.h
> +++ b/arch/mips/include/asm/cache.h
> @@ -33,4 +33,25 @@
> #define ARCH_DMA_MINALIGN 128
> #endif
>
> +/*
> + * Descriptor for a cache
> + */
> +struct cache_desc {
> + unsigned int size; /* total size */
> + unsigned int waysize; /* Bytes per way */
> + unsigned short sets; /* Number of lines per set */
> + unsigned char ways; /* Number of ways */
> + unsigned char linesz; /* Size of line in bytes */
> +};
> +
> +#define cache_op(op,addr) \
> + __asm__ __volatile__( \
> + " .set push \n" \
> + " .set noreorder \n" \
> + " .set mips64\n\t \n" \
> + " cache %0, %1 \n" \
> + " .set pop \n" \
> + : \
> + : "i" (op), "R" (*(unsigned char *)(addr)))
> +
> #endif /* __MIPS_CACHE_H__ */
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 025012a..1b82c61 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
> */
> extern inline phys_addr_t virt_to_phys(volatile void * address)
> {
> +#ifndef CONFIG_64BIT
> return CPHYSADDR(address);
> +#else
> + return XPHYSADDR(address);
> +#endif
> }
>
> extern inline void * phys_to_virt(unsigned long address)
> {
> - return (void *)KSEG0ADDR(address);
> +#ifndef CONFIG_64BIT
> + return (void *)KSEG0ADDR(address);
> +#else
> + return (void *)CKSEG0ADDR(address);
> +#endif
> }
>
> /*
> @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
> */
> extern inline unsigned long virt_to_bus(volatile void * address)
> {
> +#ifndef CONFIG_64BIT
> return CPHYSADDR(address);
> +#else
> + return XPHYSADDR(address);
> +#endif
> }
>
> extern inline void * bus_to_virt(unsigned long address)
> {
> +#ifndef CONFIG_64BIT
> return (void *)KSEG0ADDR(address);
> +#else
> + return (void *)CKSEG0ADDR(address);
> +#endif
> }
>
> /*
> diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
> index 879aae2..0da1dde 100644
> --- a/arch/mips/include/asm/posix_types.h
> +++ b/arch/mips/include/asm/posix_types.h
> @@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
> typedef int __kernel_ipc_pid_t;
> typedef int __kernel_uid_t;
> typedef int __kernel_gid_t;
> -typedef unsigned int __kernel_size_t;
> -typedef int __kernel_ssize_t;
> -typedef int __kernel_ptrdiff_t;
> +#ifndef CONFIG_MIPS64
> + typedef unsigned int __kernel_size_t;
> + typedef int __kernel_ssize_t;
> + typedef int __kernel_ptrdiff_t;
> +#else
> +typedef unsigned long __kernel_size_t;
> +typedef long __kernel_ssize_t;
> +typedef long __kernel_ptrdiff_t;
> +#endif
> typedef long __kernel_time_t;
> typedef long __kernel_suseconds_t;
> typedef long __kernel_clock_t;
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-24 0:23 ` Daniel Schwierzeck
2012-08-20 14:22 ` [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64 Zhizhou Zhang
` (7 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
This patch add qemu-mips64 config. And here uses qemu-mips board rather
then a new board qemu-mips64 for the sake of reduce code copying. Below
are the changes:
config.mk: We must define CONFIG_SYS_TEXT_BASE in configs/*.h, not
here, so remove this file.
u-boot.lds: add mips64 link statements.
boards.cfg: add mips64 cpu define.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
board/qemu-mips/config.mk | 10 ---
board/qemu-mips/u-boot.lds | 8 ++
boards.cfg | 1 +
include/configs/qemu-mips.h | 3 +
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 183 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..0000000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips")
+#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) >> 3;
+#else
num_got_entries = (__got_end - __got_start) >> 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..a6806b8 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,6 +379,7 @@ M5485GFE m68k mcf547x_8x m548xevb freescale -
M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips
+qemu_mips64 mips mips64 qemu-mips - - qemu-mips64
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 306c173..bb85bbe 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -135,6 +135,9 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
+//#define CONFIG_SYS_TEXT_BASE 0x80001000 /* RAM Version */
+
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 0000000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux\0" \
+ "load=tftp ffffffff80500000 ${u-boot}\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND ""
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */
+
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_CMD_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+/* The following #defines are needed to get flash environment right */
+#undef CONFIG_SYS_TEXT_BASE
+//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */
+#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#define MEM_SIZE 128
+
+#undef CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_LZA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs
2012-08-20 14:22 ` [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs Zhizhou Zhang
@ 2012-08-24 0:23 ` Daniel Schwierzeck
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-24 0:23 UTC (permalink / raw)
To: u-boot
2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> This patch add qemu-mips64 config. And here uses qemu-mips board rather
> then a new board qemu-mips64 for the sake of reduce code copying. Below
> are the changes:
> config.mk: We must define CONFIG_SYS_TEXT_BASE in configs/*.h, not
> here, so remove this file.
> u-boot.lds: add mips64 link statements.
> boards.cfg: add mips64 cpu define.
>
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> board/qemu-mips/config.mk | 10 ---
> board/qemu-mips/u-boot.lds | 8 ++
> boards.cfg | 1 +
> include/configs/qemu-mips.h | 3 +
> include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 183 insertions(+), 10 deletions(-)
> delete mode 100644 board/qemu-mips/config.mk
> create mode 100644 include/configs/qemu-mips64.h
>
> diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
> deleted file mode 100644
> index 27cd34a..0000000
> --- a/board/qemu-mips/config.mk
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#
> -# Qemu -M mips system emulator
> -# See http://fabrice.bellard.free.fr/qemu
> -#
> -
> -# ROM version
> -CONFIG_SYS_TEXT_BASE = 0xbfc00000
> -
> -# RAM version
> -#CONFIG_SYS_TEXT_BASE = 0x80001000
> diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
> index 9460b20..06db68d 100644
> --- a/board/qemu-mips/u-boot.lds
> +++ b/board/qemu-mips/u-boot.lds
> @@ -24,7 +24,11 @@
> /*
> OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
> */
> +#if defined(CONFIG_64BIT)
> +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips")
this is still wrong. We ideally want to support qemu_mips64 and qemu_mips64el.
Please use
OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
> +#else
> OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
> +#endif
> OUTPUT_ARCH(mips)
> ENTRY(_start)
> SECTIONS
> @@ -63,7 +67,11 @@ SECTIONS
> }
>
> uboot_end_data = .;
> +#if defined(CONFIG_64BIT)
> + num_got_entries = (__got_end - __got_start) >> 3;
> +#else
> num_got_entries = (__got_end - __got_start) >> 2;
> +#endif
>
> . = ALIGN(4);
> .sbss : { *(.sbss*) }
> diff --git a/boards.cfg b/boards.cfg
> index fdb84ad..a6806b8 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -379,6 +379,7 @@ M5485GFE m68k mcf547x_8x m548xevb freescale -
> M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
> microblaze-generic microblaze microblaze microblaze-generic xilinx
> qemu_mips mips mips32 qemu-mips - - qemu-mips
> +qemu_mips64 mips mips64 qemu-mips - - qemu-mips64
please use following to support both endianess types
qemu_mips64 mips mips64 qemu-mips
- - qemu-mips64:SYS_BIG_ENDIAN
qemu_mips64el mips mips64 qemu-mips
- - qemu-mips64:SYS_LITTLE_ENDIAN
> vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
> vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
> vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
> diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
> index 306c173..bb85bbe 100644
> --- a/include/configs/qemu-mips.h
> +++ b/include/configs/qemu-mips.h
> @@ -135,6 +135,9 @@
> #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> #define CONFIG_SYS_MONITOR_LEN (192 << 10)
>
> +#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
> +//#define CONFIG_SYS_TEXT_BASE 0x80001000 /* RAM Version */
no C++ style comments. Actually you could drop that line.
> +
> #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
>
> /* We boot from this flash, selected with dip switch */
> diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
> new file mode 100644
> index 0000000..2f39494
> --- /dev/null
> +++ b/include/configs/qemu-mips64.h
> @@ -0,0 +1,171 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * This file contains the configuration parameters for qemu-mips64 target.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
> +#define CONFIG_64BIT 1
you already defined that in arch/mips/cpu/mips64/config.mk
> +#define CONFIG_QEMU_MIPS 1
> +#define CONFIG_MISC_INIT_R
you can drop the 1's on all config options which only enable something.
> +
> +/*IP address is default used by Qemu*/
> +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
> +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
> +
> +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
> +
> +#define CONFIG_BAUDRATE 115200
> +
> +/* valid baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
> +#undef CONFIG_BOOTARGS
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "addmisc=setenv bootargs ${bootargs} " \
> + "console=ttyS0,${baudrate} " \
> + "panic=1\0" \
> + "bootfile=/tftpboot/vmlinux\0" \
> + "load=tftp ffffffff80500000 ${u-boot}\0" \
> + ""
> +
> +#define CONFIG_BOOTCOMMAND ""
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#define CONFIG_DP83902A
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +#undef CONFIG_CMD_LOADB
> +#undef CONFIG_CMD_LOADS
> +#define CONFIG_CMD_DHCP
> +
> +#define CONFIG_DRIVER_NE2000
> +#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300)
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK 115200
> +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
> +#define CONFIG_CONS_INDEX 1
> +
> +#define CONFIG_CMD_IDE
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_SYS_IDE_MAXBUS 2
> +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
> +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
> +#define CONFIG_SYS_ATA_DATA_OFFSET (0)
> +#define CONFIG_SYS_ATA_REG_OFFSET (0)
> +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
> +
> +#define CONFIG_SYS_IDE_MAXDEVICE (4)
> +
> +#define CONFIG_CMD_RARP
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +
> +#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */
> +
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +
> +#define CONFIG_SYS_MALLOC_LEN 128*1024
> +
> +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
> +
> +#define CONFIG_SYS_MHZ 132
> +
> +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */
> +
> +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */
> +
> +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
> +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +#define CONFIG_CMD_NO_FLASH
> +#define CONFIG_SYS_NO_FLASH
> +#undef CONFIG_CMD_IMLS
> +
> +/* The following #defines are needed to get flash environment right */
> +#undef CONFIG_SYS_TEXT_BASE
> +//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */
> +#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> +#define CONFIG_ENV_IS_NOWHERE 1
> +
> +/* Address and size of Primary Environment Sector */
> +#define CONFIG_ENV_SIZE 0x8000
> +
> +#define CONFIG_ENV_OVERWRITE 1
> +
> +#define MEM_SIZE 128
> +
> +#undef CONFIG_MEMSIZE_IN_BYTES
> +
> +#define CONFIG_LZA
> +
> +/*-----------------------------------------------------------------------
> + * Cache Configuration
> + */
> +#define CONFIG_SYS_DCACHE_SIZE 16384
> +#define CONFIG_SYS_ICACHE_SIZE 16384
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +
> +#endif /* __CONFIG_H */
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (2 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-24 0:23 ` Daniel Schwierzeck
2012-08-20 14:22 ` [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (6 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
I think copy mips.lds to mips64.lds with only one line changed is not
good. So I disable it in top Makefile.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Makefile b/Makefile
index 5ce5cc3..626d888 100644
--- a/Makefile
+++ b/Makefile
@@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep
sinclude $(obj)include/autoconf.mk
ifndef CONFIG_SANDBOX
+ifndef CONFIG_MIPS64
SUBDIRS += $(SUBDIR_EXAMPLES)
endif
+endif
# load ARCH, BOARD, and CPU configuration
include $(obj)include/config.mk
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
2012-08-20 14:22 ` [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64 Zhizhou Zhang
@ 2012-08-24 0:23 ` Daniel Schwierzeck
2012-08-26 12:45 ` Zhi-zhou Zhang
0 siblings, 1 reply; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-24 0:23 UTC (permalink / raw)
To: u-boot
2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> I think copy mips.lds to mips64.lds with only one line changed is not
> good. So I disable it in top Makefile.
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> Makefile | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Makefile b/Makefile
> index 5ce5cc3..626d888 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep
> sinclude $(obj)include/autoconf.mk
>
> ifndef CONFIG_SANDBOX
> +ifndef CONFIG_MIPS64
> SUBDIRS += $(SUBDIR_EXAMPLES)
> endif
> +endif
>
> # load ARCH, BOARD, and CPU configuration
> include $(obj)include/config.mk
> --
> 1.7.9.5
>
NAK.
Please do what you have done in v1 of your patch series. This is possible now
if you use current master of git://git.denx.de/u-boot-mips.git.
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
2012-08-24 0:23 ` Daniel Schwierzeck
@ 2012-08-26 12:45 ` Zhi-zhou Zhang
2012-08-26 13:33 ` Daniel Schwierzeck
0 siblings, 1 reply; 24+ messages in thread
From: Zhi-zhou Zhang @ 2012-08-26 12:45 UTC (permalink / raw)
To: u-boot
On Fri, Aug 24, 2012 at 8:23 AM, Daniel Schwierzeck <
daniel.schwierzeck@gmail.com> wrote:
> 2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> > I think copy mips.lds to mips64.lds with only one line changed is not
> > good. So I disable it in top Makefile.
> > Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> > ---
> > Makefile | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/Makefile b/Makefile
> > index 5ce5cc3..626d888 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep
> > sinclude $(obj)include/autoconf.mk
> >
> > ifndef CONFIG_SANDBOX
> > +ifndef CONFIG_MIPS64
> > SUBDIRS += $(SUBDIR_EXAMPLES)
> > endif
> > +endif
> >
> > # load ARCH, BOARD, and CPU configuration
> > include $(obj)include/config.mk
> > --
> > 1.7.9.5
> >
>
> NAK.
>
> Please do what you have done in v1 of your patch series. This is possible
> now
> if you use current master of git://git.denx.de/u-boot-mips.git.
>
> --
> Best regards,
> Daniel
>
when I add below in examples/standalone/mips.lds,
#ifdef CONFIG_64BIT
OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips",
"elf64-tradlittlemips")
#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
"elf32-tradlittlemips")
#endif
I will get a error:
/home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27:
ignoring invalid character `#' in expression
/home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27:
syntax error
So I find these in top Makefile:
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P -
<$^ >$@
It seems that I can't make mips.lds configurable without a lot
modifications in example/standalone/Makefile.
So could you give a tip?
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
2012-08-26 12:45 ` Zhi-zhou Zhang
@ 2012-08-26 13:33 ` Daniel Schwierzeck
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-26 13:33 UTC (permalink / raw)
To: u-boot
2012/8/26 Zhi-zhou Zhang <etou.zh@gmail.com>:
>
>
> On Fri, Aug 24, 2012 at 8:23 AM, Daniel Schwierzeck
> <daniel.schwierzeck@gmail.com> wrote:
>>
>> 2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
>> > I think copy mips.lds to mips64.lds with only one line changed is not
>> > good. So I disable it in top Makefile.
>> > Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
>> > ---
>> > Makefile | 2 ++
>> > 1 file changed, 2 insertions(+)
>> >
>> > diff --git a/Makefile b/Makefile
>> > index 5ce5cc3..626d888 100644
>> > --- a/Makefile
>> > +++ b/Makefile
>> > @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep
>> > sinclude $(obj)include/autoconf.mk
>> >
>> > ifndef CONFIG_SANDBOX
>> > +ifndef CONFIG_MIPS64
>> > SUBDIRS += $(SUBDIR_EXAMPLES)
>> > endif
>> > +endif
>> >
>> > # load ARCH, BOARD, and CPU configuration
>> > include $(obj)include/config.mk
>> > --
>> > 1.7.9.5
>> >
>>
>> NAK.
>>
>> Please do what you have done in v1 of your patch series. This is possible
>> now
>> if you use current master of git://git.denx.de/u-boot-mips.git.
>>
>> --
>> Best regards,
>> Daniel
>
>
> when I add below in examples/standalone/mips.lds,
> #ifdef CONFIG_64BIT
> OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips",
> "elf64-tradlittlemips")
> #else
> OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
> "elf32-tradlittlemips")
> #endif
> I will get a error:
> /home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27:
> ignoring invalid character `#' in expression
> /home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27:
> syntax error
>
> So I find these in top Makefile:
> $(obj)u-boot.lds: $(LDSCRIPT)
> $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P -
> <$^ >$@
> It seems that I can't make mips.lds configurable without a lot modifications
> in example/standalone/Makefile.
> So could you give a tip?
yes, in my previous comment I thought that mips.lds is also
preprocessed like u-boot.lds.
But sadly that is not the case. You have added a mips64.lds in your
first patch series.
I guess that was already the correct solution without changing
standalone/Makefile.
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 0/4] add mips64 cpu support
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (3 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64 Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
` (5 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
This patch add mips64 cpu support.
Changes in V3:
- merge related files into one patch, no longer one file one patch.
- add detailed commit message.
- remove standalone example. it's too complicate.
Zhizhou Zhang (4):
[MIPS] Add support for MIPS64 cpus
[MIPS] add mips64 support in mips head files
[MIPS] Add qemu-mips building configs
[MIPS] Disable standalone while building MIPS64
Makefile | 2 +
arch/mips/cpu/mips64/Makefile | 47 +++++++
arch/mips/cpu/mips64/config.mk | 39 ++++++
arch/mips/cpu/mips64/cpu.c | 124 +++++++++++++++++
arch/mips/cpu/mips64/interrupts.c | 39 ++++++
arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/time.c | 86 ++++++++++++
arch/mips/include/asm/addrspace.h | 2 +-
arch/mips/include/asm/cache.h | 21 +++
arch/mips/include/asm/io.h | 18 ++-
arch/mips/include/asm/posix_types.h | 12 +-
board/qemu-mips/config.mk | 10 --
board/qemu-mips/u-boot.lds | 8 ++
boards.cfg | 1 +
include/configs/qemu-mips.h | 3 +
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++
16 files changed, 824 insertions(+), 15 deletions(-)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 include/configs/qemu-mips64.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (4 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files Zhizhou Zhang
` (4 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
These files are derived from arch/mips/cpu/mips32/*. Howerver some
Changes are made:
*.S: changes ABI o32 to n64
config.mk: add mips64 building cflags
cpu.c: add cache size probe
interrupts.c: implement enable_interrupts and disable_interrupts
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/cpu/mips64/Makefile | 47 +++++++
arch/mips/cpu/mips64/config.mk | 39 ++++++
arch/mips/cpu/mips64/cpu.c | 124 ++++++++++++++++++
arch/mips/cpu/mips64/interrupts.c | 39 ++++++
arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/time.c | 86 +++++++++++++
6 files changed, 591 insertions(+)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
new file mode 100644
index 0000000..335fe88
--- /dev/null
+++ b/arch/mips/cpu/mips64/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS-y = cpu.o interrupts.o time.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
new file mode 100644
index 0000000..26f79e6
--- /dev/null
+++ b/arch/mips/cpu/mips64/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+ENDIANNESS = -EL
+
+MIPSFLAGS += $(ENDIANNESS)
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+PLATFORM_LDFLAGS += -m elf64ltsmip
+
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 0000000..348ccfe
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+#include <linux/compiler.h>
+
+void __weak _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, "*** reset failed ***\n");
+ return 0;
+}
+
+static struct cache_desc icache, dcache;
+
+void cache_probe(void)
+{
+ int config, lsize;
+
+ config = read_c0_config1();
+ lsize = (config >> 19) & 7;
+ if (lsize) { /* icache present */
+ icache.linesz = 2 << lsize;
+ icache.sets = 32 << (((config >> 22) + 1) & 7);
+ icache.ways = 1 + ((config >> 16) & 7);
+ icache.size = icache.sets *
+ icache.ways *
+ icache.linesz;
+ }
+
+ lsize = (config >> 10) & 7;
+ if (lsize) { /* dcache present */
+ dcache.linesz = 2 << lsize;
+ dcache.sets = 32 << (((config >> 13) + 1) & 7);
+ dcache.ways = 1 + ((config >> 7) & 7);
+ dcache.size = dcache.sets *
+ dcache.ways *
+ dcache.linesz;
+ }
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long addr, aend;
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ addr = start_addr & ~(icache.linesz - 1);
+ aend = (start_addr + size - 1) & ~(icache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += icache.linesz;
+ }
+
+ addr = start_addr & ~(dcache.linesz - 1);
+ aend = (start_addr + size - 1) & ~(dcache.linesz - 1);
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr & ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long addr = start_addr & ~(dcache.linesz - 1);
+ unsigned long aend = (stop - 1) & ~(dcache.linesz - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += dcache.linesz;
+ }
+}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 0000000..f661fb0
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status | ST0_IE);
+}
+
+int disable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status & ~ST0_IE);
+ return status | ST0_IE;
+}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644
index 0000000..b8585e7
--- /dev/null
+++ b/arch/mips/cpu/mips64/start.S
@@ -0,0 +1,256 @@
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ * Copyright (c) 2012 Zhi-zhou Zhang <etou.zh@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+ dla t9, cache_probe
+ jalr t9
+ nop
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ li t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ li t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 0000000..350896a
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return (timestamp - base);
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (5 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs Zhizhou Zhang
` (3 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
The most important difference between mips32 and mips64 is the address
space. changes in addrspace.h and io.h are for this sake. And this patch
add cache discribe struct in cache.h, and make compatible to mips64 of
some types in posix_types.h.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/include/asm/addrspace.h | 2 +-
arch/mips/include/asm/cache.h | 21 +++++++++++++++++++++
arch/mips/include/asm/io.h | 18 +++++++++++++++++-
arch/mips/include/asm/posix_types.h | 12 +++++++++---
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 5406d5d..e41b9b4 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -33,4 +33,25 @@
#define ARCH_DMA_MINALIGN 128
#endif
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int size; /* total size */
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets; /* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+};
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips64\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..1b82c61 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
- return (void *)KSEG0ADDR(address);
+#ifndef CONFIG_64BIT
+ return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 879aae2..0da1dde 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
+#ifndef CONFIG_MIPS64
+ typedef unsigned int __kernel_size_t;
+ typedef int __kernel_ssize_t;
+ typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (6 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-20 14:22 ` [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64 Zhizhou Zhang
` (2 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
This patch add qemu-mips64 config. And here uses qemu-mips board rather
then a new board qemu-mips64 for the sake of reduce code copying. Below
are the changes:
config.mk: We must define CONFIG_SYS_TEXT_BASE in configs/*.h, not
here, so remove this file.
u-boot.lds: add mips64 link statements.
boards.cfg: add mips64 cpu define.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
board/qemu-mips/config.mk | 10 ---
board/qemu-mips/u-boot.lds | 8 ++
boards.cfg | 1 +
include/configs/qemu-mips.h | 3 +
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 183 insertions(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 include/configs/qemu-mips64.h
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..0000000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips")
+#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) >> 3;
+#else
num_got_entries = (__got_end - __got_start) >> 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..a6806b8 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,6 +379,7 @@ M5485GFE m68k mcf547x_8x m548xevb freescale -
M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips
+qemu_mips64 mips mips64 qemu-mips - - qemu-mips64
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 306c173..bb85bbe 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -135,6 +135,9 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
+//#define CONFIG_SYS_TEXT_BASE 0x80001000 /* RAM Version */
+
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 0000000..2f39494
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux\0" \
+ "load=tftp ffffffff80500000 ${u-boot}\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND ""
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */
+
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_CMD_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+/* The following #defines are needed to get flash environment right */
+#undef CONFIG_SYS_TEXT_BASE
+//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */
+#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#define MEM_SIZE 128
+
+#undef CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_LZA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (7 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 3/4] [MIPS] Add qemu-mips building configs Zhizhou Zhang
@ 2012-08-20 14:22 ` Zhizhou Zhang
2012-08-23 3:04 ` [U-Boot] [Patch V3 0/4] add mips64 cpu support Mike Frysinger
2012-08-24 0:21 ` Daniel Schwierzeck
10 siblings, 0 replies; 24+ messages in thread
From: Zhizhou Zhang @ 2012-08-20 14:22 UTC (permalink / raw)
To: u-boot
I think copy mips.lds to mips64.lds with only one line changed is not
good. So I disable it in top Makefile.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Makefile b/Makefile
index 5ce5cc3..626d888 100644
--- a/Makefile
+++ b/Makefile
@@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep
sinclude $(obj)include/autoconf.mk
ifndef CONFIG_SANDBOX
+ifndef CONFIG_MIPS64
SUBDIRS += $(SUBDIR_EXAMPLES)
endif
+endif
# load ARCH, BOARD, and CPU configuration
include $(obj)include/config.mk
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 0/4] add mips64 cpu support
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (8 preceding siblings ...)
2012-08-20 14:22 ` [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64 Zhizhou Zhang
@ 2012-08-23 3:04 ` Mike Frysinger
2012-08-23 14:14 ` Zhi-zhou Zhang
2012-08-24 0:21 ` Daniel Schwierzeck
10 siblings, 1 reply; 24+ messages in thread
From: Mike Frysinger @ 2012-08-23 3:04 UTC (permalink / raw)
To: u-boot
On Monday 20 August 2012 10:22:22 Zhizhou Zhang wrote:
> This patch add mips64 cpu support.
> Changes in V3:
> - merge related files into one patch, no longer one file one patch.
> - add detailed commit message.
> - remove standalone example. it's too complicate.
do you keep sending these patchsets in duplicate on purpose ? your v2 and v3
series both were doubly sent.
-mike
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^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [Patch V3 0/4] add mips64 cpu support
2012-08-23 3:04 ` [U-Boot] [Patch V3 0/4] add mips64 cpu support Mike Frysinger
@ 2012-08-23 14:14 ` Zhi-zhou Zhang
0 siblings, 0 replies; 24+ messages in thread
From: Zhi-zhou Zhang @ 2012-08-23 14:14 UTC (permalink / raw)
To: u-boot
On Thu, Aug 23, 2012 at 11:04 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Monday 20 August 2012 10:22:22 Zhizhou Zhang wrote:
> > This patch add mips64 cpu support.
> > Changes in V3:
> > - merge related files into one patch, no longer one file one patch.
> > - add detailed commit message.
> > - remove standalone example. it's too complicate.
>
> do you keep sending these patchsets in duplicate on purpose ? your v2 and
> v3
> series both were doubly sent.
> -mike
>
I'm sorry, I'm a fresh to mail-list. I used to think I should send a patch
diff from master branch.
Thanks for you guidance.
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [Patch V3 0/4] add mips64 cpu support
2012-08-20 14:22 [U-Boot] [Patch V3 0/4] add mips64 cpu support Zhizhou Zhang
` (9 preceding siblings ...)
2012-08-23 3:04 ` [U-Boot] [Patch V3 0/4] add mips64 cpu support Mike Frysinger
@ 2012-08-24 0:21 ` Daniel Schwierzeck
10 siblings, 0 replies; 24+ messages in thread
From: Daniel Schwierzeck @ 2012-08-24 0:21 UTC (permalink / raw)
To: u-boot
2012/8/20 Zhizhou Zhang <etou.zh@gmail.com>:
> This patch add mips64 cpu support.
> Changes in V3:
> - merge related files into one patch, no longer one file one patch.
> - add detailed commit message.
> - remove standalone example. it's too complicate.
>
> Zhizhou Zhang (4):
> [MIPS] Add support for MIPS64 cpus
> [MIPS] add mips64 support in mips head files
> [MIPS] Add qemu-mips building configs
> [MIPS] Disable standalone while building MIPS64
>
looks better now, but there are still some issues:
- please replace [MIPS] by MIPS:
- always check each patch with checkpatch.pl in tools directory anf
fix the warnings
Please rework and base your patches on
git://git.denx.de/u-boot-mips.git. I have prepared
some patches which rework the handling of endianess flags and
CONFIG_STANDALONE_LOAD_ADDR.
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 24+ messages in thread