From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tom Rini <trini@ti.com>
Date: Thu, 30 Aug 2012 15:25:05 -0700
Subject: [U-Boot] [PATCHv1] ARM: Add Altera SOCFPGA Cyclone5
In-Reply-To: <20120830204211.GA6356@elf.ucw.cz>
References: <503B98ED.3090407@ti.com> <20120829134154.GA13606@elf.ucw.cz>
	<20120829182645.GB3450@bill-the-cat>
	<20120829232153.GA23417@elf.ucw.cz> <503EAD32.90806@ti.com>
	<20120830171842.GD5980@elf.ucw.cz> <503FA436.7090201@ti.com>
	<20120830180532.GA29900@elf.ucw.cz> <503FB15B.5040507@ti.com>
	<20120830204211.GA6356@elf.ucw.cz>
Message-ID: <20120830222505.GA17506@bill-the-cat>
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On Thu, Aug 30, 2012 at 10:42:11PM +0200, Pavel Machek wrote:
> Hi!
> 
> > >>> spl_ram_load_image... will I need to create some kind of #ifdef? Or
> > >>> would #ifdef BOOT_DEVICE_RAM do the trick?
> > >>
> > >> Good point, yes, we should add CONFIG_SPL_RAM_DEVICE and document it in
> > >> docs/README.SPL and the toplevel README.
> > > 
> > > Ok, something like this? Posting separately, maybe it makes sense to
> > > merge to your PATCH v6...?
> > 
> > Sure, just include the actual spl_ram_load_image bits as well and I'll
> > pick it up.
> 
> Here you go.

With the multi-line comment fixed up, queued for my v6.

-- 
Tom