From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Cache alignment warnings on Tegra (ARM)
Date: Thu, 13 Sep 2012 00:38:03 +0200 [thread overview]
Message-ID: <201209130038.03513.marex@denx.de> (raw)
In-Reply-To: <5050BCFF.9030506@wwwdotorg.org>
Dear Stephen Warren,
> On 09/12/2012 10:19 AM, Tom Warren wrote:
> > Folks,
> >
> > Stephen Warren has posted an internal bug regarding the cache
> > alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
> > the gist:
> >
> > Executing "mmc dev 0" still yields cache warnings:
> >
> > Tegra20 (Harmony) # mmc dev 0
> > ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908
> > mmc0 is current device
>
> ...
>
> > There have been patches in the past (IIRC) that have tried to ensure
> > all callers (FS, MMC driver, USB driver, etc.) force their buffers to
> > the appropriate alignment, but I don't know that we can ever correct
> > every instance, now or in the future.
> >
> > Can we start a discussion about what we can do about this warning?
> > Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS,
> > etc.) where Stephen put his #if 0's would be one approach, or changing
> > the printf() to a debug(), perhaps. As far as I can tell, these
> > alignment 'errors' don't seem to produce bad data in the transfer.
>
> I don't think simply turning off the warning is the correct approach; I
> believe they represent real problems that can in fact cause data
> corruption. I don't believe we have any choice other than to fully solve
> the root-cause.
Try CONFIG_MMC_BOUNCE_BUFFER or what it was called ... see
inclued/configs/m28evk.h , I use it there.
Best regards,
Marek Vasut
next prev parent reply other threads:[~2012-09-12 22:38 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 16:19 [U-Boot] Cache alignment warnings on Tegra (ARM) Tom Warren
2012-09-12 16:49 ` Stephen Warren
2012-09-12 22:38 ` Marek Vasut [this message]
2012-09-12 23:10 ` Stephen Warren
2012-09-12 23:42 ` Marek Vasut
2012-09-14 15:53 ` Simon Glass
2012-09-15 20:01 ` Thierry Reding
2012-09-15 20:11 ` Marek Vasut
2012-09-15 20:41 ` Thierry Reding
2012-09-15 20:56 ` Marek Vasut
2012-09-16 2:45 ` Simon Glass
2012-09-16 6:49 ` Thierry Reding
2012-09-17 21:39 ` Simon Glass
2012-09-18 14:54 ` Thierry Reding
2012-09-18 18:24 ` Simon Glass
2012-09-18 18:37 ` Marek Vasut
2012-09-18 19:00 ` Thierry Reding
2012-09-18 19:21 ` Marek Vasut
2012-09-18 19:29 ` Thierry Reding
2012-09-18 19:36 ` Marek Vasut
2012-09-18 20:04 ` Thierry Reding
2012-09-18 20:28 ` Simon Glass
2012-09-18 21:21 ` Marek Vasut
2012-09-18 22:42 ` Simon Glass
2012-09-18 22:44 ` Marek Vasut
2012-09-19 5:45 ` Thierry Reding
2012-09-18 21:20 ` Marek Vasut
2012-09-19 5:46 ` Thierry Reding
2012-09-15 20:19 ` Thierry Reding
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