[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Michal Simek]

The driver is used on Xilinx Zynq platform.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
    Rename driver name
    Remove driver description
---
 drivers/serial/Makefile      |    1 +
 drivers/serial/serial_zynq.c |  200 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 201 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/serial_zynq.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..dfc22a4 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
 COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 
 ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
new file mode 100644
index 0000000..c49da3b
--- /dev/null
+++ b/drivers/serial/serial_zynq.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+
+#define ZYNQ_UART_SR_TXFULL	0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_RXEMPTY	0x00000002 /* RX FIFO empty */
+
+#define ZYNQ_UART_CR_TX_EN	0x00000010 /* TX enabled */
+#define ZYNQ_UART_CR_RX_EN	0x00000004 /* RX enabled */
+#define ZYNQ_UART_CR_TXRST	0x00000002 /* TX logic reset */
+#define ZYNQ_UART_CR_RXRST	0x00000001 /* RX logic reset */
+
+#define ZYNQ_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
+
+/* Some clock/baud constants */
+#define ZYNQ_UART_BDIV	15 /* Default/reset BDIV value */
+#define ZYNQ_UART_BASECLK	3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+	u32 control; /* Control Register [8:0] */
+	u32 mode; /* Mode Register [10:0] */
+	u32 reserved1[4];
+	u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+	u32 reserved2[4];
+	u32 channel_sts; /* Channel Status [11:0] */
+	u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+	u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[2] = {
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+	[0] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+	[1] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#endif
+};
+
+struct xdfuart_params {
+	u32 baudrate;
+	u32 clock;
+};
+
+static struct xdfuart_params xdf_ports_param[2] = {
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
+	[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
+	[0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
+	[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
+	[1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
+#endif
+};
+
+/* Set up the baud rate in gd struct */
+static void xdfuart_serial_setbrg(const int port)
+{
+	/* Calculation results. */
+	unsigned int calc_bauderror, bdiv, bgen;
+	unsigned long calc_baud = 0;
+	unsigned long baud = xdf_ports_param[port].baudrate;
+	unsigned long clock = xdf_ports_param[port].clock;
+	struct xdfuart *regs = xdf_ports[port];
+
+	/*                master clock
+	 * Baud rate = ------------------
+	 *              bgen * (bdiv + 1)
+	 *
+	 * Find acceptable values for baud generation.
+	 */
+	for (bdiv = 4; bdiv < 255; bdiv++) {
+		bgen = clock / (baud * (bdiv + 1));
+		if (bgen < 2 || bgen > 65535)
+			continue;
+
+		calc_baud = clock / (bgen * (bdiv + 1));
+
+		/*
+		 * Use first calculated baudrate with
+		 * an acceptable (<3%) error
+		 */
+		if (baud > calc_baud)
+			calc_bauderror = baud - calc_baud;
+		else
+			calc_bauderror = calc_baud - baud;
+		if (((calc_bauderror * 100) / baud) < 3)
+			break;
+	}
+
+	writel(bdiv, &regs->baud_rate_divider);
+	writel(bgen, &regs->baud_rate_gen);
+}
+
+/* Initialize the UART, with...some settings. */
+static int xdfuart_serial_init(const int port)
+{
+	struct xdfuart *regs = xdf_ports[port];
+
+	if (!regs)
+		return -1;
+
+	/* RX/TX enabled & reset */
+	writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
+					ZYNQ_UART_CR_RXRST, &regs->control);
+	writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
+	xdfuart_serial_setbrg(port);
+
+	return 0;
+}
+
+static void xdfuart_serial_putc(const char c, const int port)
+{
+	struct xdfuart *regs = xdf_ports[port];
+
+	while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+		WATCHDOG_RESET();
+
+	if (c == '\n') {
+		writel('\r', &regs->tx_rx_fifo);
+		while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+			WATCHDOG_RESET();
+	}
+	writel(c, &regs->tx_rx_fifo);
+}
+
+static void xdfuart_serial_puts(const char *s, const int port)
+{
+	while (*s)
+		xdfuart_serial_putc(*s++, port);
+}
+
+static int xdfuart_serial_tstc(const int port)
+{
+	struct xdfuart *regs = xdf_ports[port];
+
+	return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
+}
+
+static int xdfuart_serial_getc(const int port)
+{
+	struct xdfuart *regs = xdf_ports[port];
+
+	while (!xdfuart_serial_tstc(port))
+		WATCHDOG_RESET();
+	return readl(&regs->tx_rx_fifo);
+}
+
+int serial_init(void)
+{
+	return xdfuart_serial_init(0);
+}
+
+void serial_setbrg(void)
+{
+	xdfuart_serial_setbrg(0);
+}
+
+void serial_putc(const char c)
+{
+	xdfuart_serial_putc(c, 0);
+}
+
+void serial_puts(const char *s)
+{
+	xdfuart_serial_puts(s, 0);
+}
+
+int serial_getc(void)
+{
+	return xdfuart_serial_getc(0);
+}
+
+int serial_tstc(void)
+{
+	return xdfuart_serial_tstc(0);
+}
-- 
1.7.0.4

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Michal Simek]

Device driver for Zynq Gem IP.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>

---
v2: Remove phylib protection
    Rename driver file name xilinx_gem to zynq_gem
    Rename XEMACPSS to ZYNQ_GEM
    Rename gemac_priv to zynq_gem_priv
    Rename gem_regs to zynq_gem_regs
    Add zynq_ prefix to several functions
    Remove phy detection
    Rename driver name XGem to Gem
    Change setup_mac function to reflect u-boot style
---
 drivers/net/Makefile   |    1 +
 drivers/net/zynq_gem.c |  453 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/netdev.h       |    2 +-
 3 files changed, 455 insertions(+), 1 deletions(-)
 create mode 100644 drivers/net/zynq_gem.c

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 430f90c..b298588 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -79,6 +79,7 @@ COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
 		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
+COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
 
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
new file mode 100644
index 0000000..d62a493
--- /dev/null
+++ b/drivers/net/zynq_gem.c
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2011 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * Based on Xilinx gmac driver:
+ * (C) Copyright 2011 Xilinx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <miiphy.h>
+
+#if !defined(CONFIG_PHYLIB)
+# error XILINX_GEM_ETHERNET requires PHYLIB
+#endif
+
+/* Bit/mask specification */
+#define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
+#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK	0x20000000 /* read operation */
+#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK	0x10000000 /* write operation */
+#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK	23 /* Shift bits for PHYAD */
+#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK	18 /* Shift bits for PHREG */
+
+#define ZYNQ_GEM_RXBUF_EOF_MASK		0x00008000 /* End of frame. */
+#define ZYNQ_GEM_RXBUF_SOF_MASK		0x00004000 /* Start of frame. */
+#define ZYNQ_GEM_RXBUF_LEN_MASK		0x00003FFF /* Mask for length field */
+
+#define ZYNQ_GEM_RXBUF_WRAP_MASK	0x00000002 /* Wrap bit, last BD */
+#define ZYNQ_GEM_RXBUF_NEW_MASK		0x00000001 /* Used bit.. */
+#define ZYNQ_GEM_RXBUF_ADD_MASK		0xFFFFFFFC /* Mask for address */
+
+/* Wrap bit, last descriptor */
+#define ZYNQ_GEM_TXBUF_WRAP_MASK	0x40000000
+#define ZYNQ_GEM_TXBUF_LAST_MASK	0x00008000 /* Last buffer */
+
+#define ZYNQ_GEM_TXSR_HRESPNOK_MASK	0x00000100 /* Transmit hresp not OK */
+#define ZYNQ_GEM_TXSR_URUN_MASK		0x00000040 /* Transmit underrun */
+/* Transmit buffs exhausted mid frame */
+#define ZYNQ_GEM_TXSR_BUFEXH_MASK	0x00000010
+
+#define ZYNQ_GEM_NWCTRL_TXEN_MASK	0x00000008 /* Enable transmit */
+#define ZYNQ_GEM_NWCTRL_RXEN_MASK	0x00000004 /* Enable receive */
+#define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
+#define ZYNQ_GEM_NWCTRL_STARTTX_MASK	0x00000200 /* Start tx (tx_go) */
+
+#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */
+
+/* Device registers */
+struct zynq_gem_regs {
+	u32 nwctrl; /* Network Control reg */
+	u32 nwcfg; /* Network Config reg */
+	u32 nwsr; /* Network Status reg */
+	u32 reserved1;
+	u32 dmacr; /* DMA Control reg */
+	u32 txsr; /* TX Status reg */
+	u32 rxqbase; /* RX Q Base address reg */
+	u32 txqbase; /* TX Q Base address reg */
+	u32 rxsr; /* RX Status reg */
+	u32 reserved2[2];
+	u32 idr; /* Interrupt Disable reg */
+	u32 reserved3;
+	u32 phymntnc; /* Phy Maintaince reg */
+	u32 reserved4[18];
+	u32 hashl; /* Hash Low address reg */
+	u32 hashh; /* Hash High address reg */
+#define LADDR_LOW	0
+#define LADDR_HIGH	1
+	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
+	u32 match[4]; /* Type ID1 Match reg */
+	u32 reserved6[18];
+	u32 stat[44]; /* Octects transmitted Low reg - stat start */
+};
+
+/* BD descriptors */
+struct emac_bd {
+	u32 addr; /* Next descriptor pointer */
+	u32 status;
+};
+
+#define RX_BUF 3
+
+/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
+struct zynq_gem_priv {
+	struct emac_bd tx_bd;
+	struct emac_bd rx_bd[RX_BUF];
+	u32 initialized;
+	char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
+	u32 rxbd_current;
+	u32 rx_first_buf;
+	int phyaddr;
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
+
+static inline int mdio_wait(struct eth_device *dev)
+{
+	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+	u32 timeout = 200;
+
+	/* Wait till MDIO interface is ready to accept a new transaction. */
+	while (timeout && !(readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)) {
+		timeout--;
+		udelay(1);
+	}
+
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return 1;
+	}
+
+	return 0;
+}
+
+static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
+							u32 op, u16 *data)
+{
+	u32 mgtcr;
+	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+
+	if (mdio_wait(dev))
+		return 1;
+
+	/* Construct mgtcr mask for the operation */
+	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
+		(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
+		(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
+
+	/* Write mgtcr and wait for completion */
+	writel(mgtcr, &regs->phymntnc);
+
+	if (mdio_wait(dev))
+		return 1;
+
+	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
+		*data = readl(&regs->phymntnc);
+
+	return 0;
+}
+
+static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
+{
+	return phy_setup_op(dev, phy_addr, regnum,
+				ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
+}
+
+static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
+{
+	return phy_setup_op(dev, phy_addr, regnum,
+				ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
+}
+
+static int zynq_gem_setup_mac(struct eth_device *dev)
+{
+	u32 i, macaddrlow, macaddrhigh;
+	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+
+	/* Set the MAC bits [31:0] in BOT */
+	macaddrlow = dev->enetaddr[0];
+	macaddrlow |= dev->enetaddr[1] << 8;
+	macaddrlow |= dev->enetaddr[2] << 16;
+	macaddrlow |= dev->enetaddr[3] << 24;
+
+	/* Set MAC bits [47:32] in TOP */
+	macaddrhigh |= dev->enetaddr[4];
+	macaddrhigh |= dev->enetaddr[5] << 8;
+
+	for (i = 0; i < 4; i++) {
+		writel(0, &regs->laddr[i][LADDR_LOW]);
+		writel(0, &regs->laddr[i][LADDR_HIGH]);
+		/* Do not use MATCHx register */
+		writel(0, &regs->match[i]);
+	}
+
+	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
+	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
+
+	return 0;
+}
+
+static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
+{
+	int tmp;
+	int i;
+	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+	struct zynq_gem_priv *priv = dev->priv;
+	struct phy_device *phydev;
+	u32 supported = SUPPORTED_10baseT_Half |
+			SUPPORTED_10baseT_Full |
+			SUPPORTED_100baseT_Half |
+			SUPPORTED_100baseT_Full |
+			SUPPORTED_1000baseT_Half |
+			SUPPORTED_1000baseT_Full;
+
+	if (priv->initialized)
+		return 0;
+
+	/* Disable all interrupts */
+	writel(0xFFFFFFFF, &regs->idr);
+
+	/* Disable the receiver & transmitter */
+	writel(0, &regs->nwctrl);
+	writel(0, &regs->txsr);
+	writel(0, &regs->rxsr);
+	writel(0, &regs->phymntnc);
+
+	/* Clear the Hash registers for the mac address pointed by AddressPtr */
+	writel(0x0, &regs->hashl);
+	/* Write bits [63:32] in TOP */
+	writel(0x0, &regs->hashh);
+
+	/* Clear all counters */
+	for (i = 0; i <= (sizeof(struct zynq_gem_regs) -
+			offsetof(struct zynq_gem_regs, stat)) / 4; i++)
+		readl(&regs->stat[i]);
+
+	/* Setup RxBD space */
+	memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
+	/* Create the RxBD ring */
+	memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+
+	for (i = 0; i < RX_BUF; i++) {
+		priv->rx_bd[i].status = 0xF0000000;
+		priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
+							(i * PKTSIZE_ALIGN));
+	}
+	/* WRAP bit to last BD */
+	priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
+	/* Write RxBDs to IP */
+	writel((u32) &(priv->rx_bd), &regs->rxqbase);
+
+
+	/* MAC Setup */
+	/*
+	 *  Following is the setup for Network Configuration register.
+	 *  Bit 0:  Set for 100 Mbps operation.
+	 *  Bit 1:  Set for Full Duplex mode.
+	 *  Bit 4:  Unset to allow Copy all frames - MAC checking
+	 *  Bit 17: Set for FCS removal.
+	 *  Bits 20-18: Set with value binary 010 to divide pclk by 32
+	 *              (pclk up to 80 MHz)
+	 */
+	writel(0x000A0003, &regs->nwcfg);
+
+	/*
+	 * Following is the setup for DMA Configuration register.
+	 * Bits 4-0: To set AHB fixed burst length for DMA data operations ->
+	 *  Set with binary 00100 to use INCR4 AHB bursts.
+	 * Bits 9-8: Receiver packet buffer memory size ->
+	 *  Set with binary 11 to Use full configured addressable space (8 Kb)
+	 * Bit 10  : Transmitter packet buffer memory size ->
+	 *  Set with binary 1 to Use full configured addressable space (4 Kb)
+	 * Bits 23-16 : DMA receive buffer size in AHB system memory ->
+	 *  Set with binary 00011000 to use 1536 byte(1*max length frame/buffer)
+	 */
+	writel(0x00180704, &regs->dmacr);
+
+	/*
+	 * Following is the setup for Network Control register.
+	 * Bit 2:  Set to enable Receive operation.
+	 * Bit 3:  Set to enable Transmitt operation.
+	 * Bit 4:  Set to enable MDIO operation.
+	 */
+	tmp = readl(&regs->nwctrl);
+	/* MDIO, Rx and Tx enable */
+	tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
+	    ZYNQ_GEM_NWCTRL_TXEN_MASK;
+	writel(tmp, &regs->nwctrl);
+
+	/* interface - look at tsec */
+	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
+
+	phydev->supported &= supported;
+	phydev->advertising = phydev->supported;
+	priv->phydev = phydev;
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	priv->initialized = 1;
+	return 0;
+}
+
+static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
+{
+	int status;
+	u32 val;
+	struct zynq_gem_priv *priv = dev->priv;
+	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+
+	if (!priv->initialized) {
+		puts("Error GMAC not initialized");
+		return -1;
+	}
+
+	/* setup BD */
+	writel((u32)&(priv->tx_bd), &regs->txqbase);
+
+	/* Setup Tx BD */
+	memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd));
+
+	priv->tx_bd.addr = (u32)ptr;
+	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK |
+						ZYNQ_GEM_TXBUF_WRAP_MASK;
+
+	/* Start transmit */
+	val = readl(&regs->nwctrl) | ZYNQ_GEM_NWCTRL_STARTTX_MASK;
+	writel(val, &regs->nwctrl);
+
+	/* Read the stat register to know if the packet has been transmitted */
+	status = readl(&regs->txsr);
+	if (status & (ZYNQ_GEM_TXSR_HRESPNOK_MASK | ZYNQ_GEM_TXSR_URUN_MASK |
+						ZYNQ_GEM_TXSR_BUFEXH_MASK)) {
+		printf("Something has gone wrong here!? Status is 0x%x.\n",
+		       status);
+	}
+
+	/* Clear Tx status register before leaving . */
+	writel(status, &regs->txsr);
+	return 0;
+}
+
+/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
+static int zynq_gem_recv(struct eth_device *dev)
+{
+	int frame_len;
+	struct zynq_gem_priv *priv = dev->priv;
+
+	if (!(priv->rx_bd[priv->rxbd_current].addr & ZYNQ_GEM_RXBUF_NEW_MASK))
+		return 0;
+
+	if (!(priv->rx_bd[priv->rxbd_current].status &
+			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
+		printf("GEM: SOF or EOF not set for last buffer received!\n");
+		return 0;
+	}
+
+	frame_len = priv->rx_bd[priv->rxbd_current].status &
+							ZYNQ_GEM_RXBUF_LEN_MASK;
+	if (frame_len) {
+		NetReceive((u8 *) (priv->rx_bd[priv->rxbd_current].addr &
+					ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
+
+		if (priv->rx_bd[priv->rxbd_current].status &
+							ZYNQ_GEM_RXBUF_SOF_MASK)
+			priv->rx_first_buf = priv->rxbd_current;
+		else {
+			priv->rx_bd[priv->rxbd_current].addr &=
+						~ZYNQ_GEM_RXBUF_NEW_MASK;
+			priv->rx_bd[priv->rxbd_current].status = 0xF0000000;
+		}
+
+		if (priv->rx_bd[priv->rxbd_current].status &
+						ZYNQ_GEM_RXBUF_EOF_MASK) {
+			priv->rx_bd[priv->rx_first_buf].addr &=
+						~ZYNQ_GEM_RXBUF_NEW_MASK;
+			priv->rx_bd[priv->rx_first_buf].status = 0xF0000000;
+		}
+
+		if ((++priv->rxbd_current) >= RX_BUF)
+			priv->rxbd_current = 0;
+
+		return frame_len;
+	}
+
+	return 0;
+}
+
+static void zynq_gem_halt(struct eth_device *dev)
+{
+	return;
+}
+
+static int zynq_gem_miiphyread(const char *devname, uchar addr,
+							uchar reg, ushort *val)
+{
+	struct eth_device *dev = eth_get_dev();
+	int ret;
+
+	ret = phyread(dev, addr, reg, val);
+	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
+	return ret;
+}
+
+static int zynq_gem_miiphy_write(const char *devname, uchar addr,
+							uchar reg, ushort val)
+{
+	struct eth_device *dev = eth_get_dev();
+
+	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
+	return phywrite(dev, addr, reg, val);
+}
+
+int zynq_gem_initialize(bd_t *bis, int base_addr)
+{
+	struct eth_device *dev;
+	struct zynq_gem_priv *priv;
+
+	dev = calloc(1, sizeof(*dev));
+	if (dev == NULL)
+		return -1;
+
+	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
+	if (dev->priv == NULL) {
+		free(dev);
+		return -1;
+	}
+	priv = dev->priv;
+
+#ifdef CONFIG_PHY_ADDR
+	priv->phyaddr = CONFIG_PHY_ADDR;
+#else
+	priv->phyaddr = -1;
+#endif
+
+	sprintf(dev->name, "Gem.%x", base_addr);
+
+	dev->iobase = base_addr;
+
+	dev->init = zynq_gem_init;
+	dev->halt = zynq_gem_halt;
+	dev->send = zynq_gem_send;
+	dev->recv = zynq_gem_recv;
+	dev->write_hwaddr = zynq_gem_setup_mac;
+
+	eth_register(dev);
+
+	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	return 1;
+}
diff --git a/include/netdev.h b/include/netdev.h
index d1aaf0c..b8d303d 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -104,7 +104,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
 int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
 						unsigned long ctrl_addr);
-
+int zynq_gem_initialize(bd_t *bis, int base_addr);
 /*
  * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
  * exported by a public hader file, we need a global definition at this point.
-- 
1.7.0.4

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Michal Simek]

On 08/16/2012 08:30 AM, Michal Simek wrote:
> Device driver for Zynq Gem IP.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
> CC: Joe Hershberger <joe.hershberger@gmail.com>
>
> ---
> v2: Remove phylib protection
>      Rename driver file name xilinx_gem to zynq_gem
>      Rename XEMACPSS to ZYNQ_GEM
>      Rename gemac_priv to zynq_gem_priv
>      Rename gem_regs to zynq_gem_regs
>      Add zynq_ prefix to several functions
>      Remove phy detection
>      Rename driver name XGem to Gem
>      Change setup_mac function to reflect u-boot style
> ---
>   drivers/net/Makefile   |    1 +
>   drivers/net/zynq_gem.c |  453 ++++++++++++++++++++++++++++++++++++++++++++++++
>   include/netdev.h       |    2 +-
>   3 files changed, 455 insertions(+), 1 deletions(-)
>   create mode 100644 drivers/net/zynq_gem.c

Joe: I am not sure if you have seen this patch. Can you please review it
and comment it.
If is ok, I would like to ask you to add this patch to your net custodian tree
or sending me your ACK.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Marek Vasut]

Dear Michal Simek,

[...]

> +static inline int mdio_wait(struct eth_device *dev)
> +{
> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
> +	u32 timeout = 200;
> +
> +	/* Wait till MDIO interface is ready to accept a new transaction. */
> +	while (timeout && !(readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)) {

I'd say, rework this to

while (--timeout) {
	if (readl() & ... )
		break;
	WATCHDOG_RESET();
}

The WATCHDOG_RESET will give you the udelay and restart the WDT if you use any. 
Also, I think it's more readable when you omit the complex condition for the 
while cycle and split it a bit.

> +		timeout--;
> +		udelay(1);
> +	}
> +
> +	if (!timeout) {
> +		printf("%s: Timeout\n", __func__);
> +		return 1;
> +	}
> +
> +	return 0;
> +}

[...]

> +static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
> +{
> +	int tmp;
> +	int i;
> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
> +	struct zynq_gem_priv *priv = dev->priv;
> +	struct phy_device *phydev;
> +	u32 supported = SUPPORTED_10baseT_Half |
> +			SUPPORTED_10baseT_Full |
> +			SUPPORTED_100baseT_Half |
> +			SUPPORTED_100baseT_Full |
> +			SUPPORTED_1000baseT_Half |
> +			SUPPORTED_1000baseT_Full;
> +
> +	if (priv->initialized)
> +		return 0;
> +
> +	/* Disable all interrupts */
> +	writel(0xFFFFFFFF, &regs->idr);
> +
> +	/* Disable the receiver & transmitter */
> +	writel(0, &regs->nwctrl);
> +	writel(0, &regs->txsr);
> +	writel(0, &regs->rxsr);
> +	writel(0, &regs->phymntnc);
> +
> +	/* Clear the Hash registers for the mac address pointed by AddressPtr */
> +	writel(0x0, &regs->hashl);
> +	/* Write bits [63:32] in TOP */
> +	writel(0x0, &regs->hashh);
> +
> +	/* Clear all counters */
> +	for (i = 0; i <= (sizeof(struct zynq_gem_regs) -
> +			offsetof(struct zynq_gem_regs, stat)) / 4; i++)

Add a const int variable and use it here so you don't have to break the for () .

> +		readl(&regs->stat[i]);
> +
> +	/* Setup RxBD space */
> +	memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
> +	/* Create the RxBD ring */
> +	memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
> +
> +	for (i = 0; i < RX_BUF; i++) {
> +		priv->rx_bd[i].status = 0xF0000000;
> +		priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
> +							(i * PKTSIZE_ALIGN));
> +	}
> +	/* WRAP bit to last BD */
> +	priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
> +	/* Write RxBDs to IP */
> +	writel((u32) &(priv->rx_bd), &regs->rxqbase);
> +
> +
> +	/* MAC Setup */
> +	/*
> +	 *  Following is the setup for Network Configuration register.
> +	 *  Bit 0:  Set for 100 Mbps operation.
> +	 *  Bit 1:  Set for Full Duplex mode.
> +	 *  Bit 4:  Unset to allow Copy all frames - MAC checking
> +	 *  Bit 17: Set for FCS removal.
> +	 *  Bits 20-18: Set with value binary 010 to divide pclk by 32
> +	 *              (pclk up to 80 MHz)
> +	 */
> +	writel(0x000A0003, &regs->nwcfg);

Well you know ... magic numbers and defined bits ;-)

> +	/*
> +	 * Following is the setup for DMA Configuration register.
> +	 * Bits 4-0: To set AHB fixed burst length for DMA data operations ->
> +	 *  Set with binary 00100 to use INCR4 AHB bursts.
> +	 * Bits 9-8: Receiver packet buffer memory size ->
> +	 *  Set with binary 11 to Use full configured addressable space (8 Kb)
> +	 * Bit 10  : Transmitter packet buffer memory size ->
> +	 *  Set with binary 1 to Use full configured addressable space (4 Kb)
> +	 * Bits 23-16 : DMA receive buffer size in AHB system memory ->
> +	 *  Set with binary 00011000 to use 1536 byte(1*max length frame/buffer)
> +	 */
> +	writel(0x00180704, &regs->dmacr);
> +
> +	/*
> +	 * Following is the setup for Network Control register.
> +	 * Bit 2:  Set to enable Receive operation.
> +	 * Bit 3:  Set to enable Transmitt operation.
> +	 * Bit 4:  Set to enable MDIO operation.
> +	 */
> +	tmp = readl(&regs->nwctrl);
> +	/* MDIO, Rx and Tx enable */
> +	tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
> +	    ZYNQ_GEM_NWCTRL_TXEN_MASK;
> +	writel(tmp, &regs->nwctrl);

setbits_le32()

> +	/* interface - look at tsec */
> +	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
> +
> +	phydev->supported &= supported;
> +	phydev->advertising = phydev->supported;
> +	priv->phydev = phydev;
> +	phy_config(phydev);
> +	phy_startup(phydev);
> +
> +	priv->initialized = 1;
> +	return 0;
> +}
> +
> +static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
> +{
> +	int status;
> +	u32 val;
> +	struct zynq_gem_priv *priv = dev->priv;
> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
> +
> +	if (!priv->initialized) {
> +		puts("Error GMAC not initialized");
> +		return -1;
> +	}
> +
> +	/* setup BD */
> +	writel((u32)&(priv->tx_bd), &regs->txqbase);
> +
> +	/* Setup Tx BD */
> +	memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd));
> +
> +	priv->tx_bd.addr = (u32)ptr;
> +	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK |
> +						ZYNQ_GEM_TXBUF_WRAP_MASK;
> +
> +	/* Start transmit */
> +	val = readl(&regs->nwctrl) | ZYNQ_GEM_NWCTRL_STARTTX_MASK;
> +	writel(val, &regs->nwctrl);

setbits_le32()

> +	/* Read the stat register to know if the packet has been transmitted */
> +	status = readl(&regs->txsr);
> +	if (status & (ZYNQ_GEM_TXSR_HRESPNOK_MASK | ZYNQ_GEM_TXSR_URUN_MASK |
> +						ZYNQ_GEM_TXSR_BUFEXH_MASK)) {

Add const int mask for the above.

> +		printf("Something has gone wrong here!? Status is 0x%x.\n",
> +		       status);
> +	}
> +
> +	/* Clear Tx status register before leaving . */
> +	writel(status, &regs->txsr);
> +	return 0;
> +}
> +
> +/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD
> */ +static int zynq_gem_recv(struct eth_device *dev)
> +{
> +	int frame_len;
> +	struct zynq_gem_priv *priv = dev->priv;
> +
> +	if (!(priv->rx_bd[priv->rxbd_current].addr & ZYNQ_GEM_RXBUF_NEW_MASK))
> +		return 0;
> +
> +	if (!(priv->rx_bd[priv->rxbd_current].status &
> +			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
> +		printf("GEM: SOF or EOF not set for last buffer received!\n");
> +		return 0;
> +	}
> +
> +	frame_len = priv->rx_bd[priv->rxbd_current].status &
> +							ZYNQ_GEM_RXBUF_LEN_MASK;

Just introduce some variable for priv->rx_bd[priv->rxbd_current] so you don't 
have such long lines

> +	if (frame_len) {
> +		NetReceive((u8 *) (priv->rx_bd[priv->rxbd_current].addr &
> +					ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
> +
> +		if (priv->rx_bd[priv->rxbd_current].status &
> +							ZYNQ_GEM_RXBUF_SOF_MASK)
> +			priv->rx_first_buf = priv->rxbd_current;
> +		else {
> +			priv->rx_bd[priv->rxbd_current].addr &=
> +						~ZYNQ_GEM_RXBUF_NEW_MASK;
> +			priv->rx_bd[priv->rxbd_current].status = 0xF0000000;
> +		}
> +
> +		if (priv->rx_bd[priv->rxbd_current].status &
> +						ZYNQ_GEM_RXBUF_EOF_MASK) {
> +			priv->rx_bd[priv->rx_first_buf].addr &=
> +						~ZYNQ_GEM_RXBUF_NEW_MASK;
> +			priv->rx_bd[priv->rx_first_buf].status = 0xF0000000;
> +		}
> +
> +		if ((++priv->rxbd_current) >= RX_BUF)
> +			priv->rxbd_current = 0;
> +
> +		return frame_len;
> +	}
> +
> +	return 0;
> +}
> +
> +static void zynq_gem_halt(struct eth_device *dev)
> +{
> +	return;

Does this need to be implemented at all ?

> +}
> +
> +static int zynq_gem_miiphyread(const char *devname, uchar addr,
> +							uchar reg, ushort *val)
> +{
> +	struct eth_device *dev = eth_get_dev();
> +	int ret;
> +
> +	ret = phyread(dev, addr, reg, val);
> +	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
> +	return ret;
> +}
> +
> +static int zynq_gem_miiphy_write(const char *devname, uchar addr,
> +							uchar reg, ushort val)
> +{
> +	struct eth_device *dev = eth_get_dev();
> +
> +	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
> +	return phywrite(dev, addr, reg, val);
> +}
> +
> +int zynq_gem_initialize(bd_t *bis, int base_addr)
> +{
> +	struct eth_device *dev;
> +	struct zynq_gem_priv *priv;
> +
> +	dev = calloc(1, sizeof(*dev));
> +	if (dev == NULL)
> +		return -1;
> +
> +	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
> +	if (dev->priv == NULL) {
> +		free(dev);
> +		return -1;
> +	}
> +	priv = dev->priv;
> +
> +#ifdef CONFIG_PHY_ADDR
> +	priv->phyaddr = CONFIG_PHY_ADDR;
> +#else
> +	priv->phyaddr = -1;
> +#endif
> +
> +	sprintf(dev->name, "Gem.%x", base_addr);
> +
> +	dev->iobase = base_addr;
> +
> +	dev->init = zynq_gem_init;
> +	dev->halt = zynq_gem_halt;
> +	dev->send = zynq_gem_send;
> +	dev->recv = zynq_gem_recv;
> +	dev->write_hwaddr = zynq_gem_setup_mac;
> +
> +	eth_register(dev);
> +
> +	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
> +	priv->bus = miiphy_get_dev_by_name(dev->name);
> +
> +	return 1;
> +}
> diff --git a/include/netdev.h b/include/netdev.h
> index d1aaf0c..b8d303d 100644
> --- a/include/netdev.h
> +++ b/include/netdev.h
> @@ -104,7 +104,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long
> base_addr, int txpp, int rxpp);
>  int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int
> flags, unsigned long ctrl_addr);
> -
> +int zynq_gem_initialize(bd_t *bis, int base_addr);
>  /*
>   * As long as the Xilinx xps_ll_temac ethernet driver has not its own
> interface * exported by a public hader file, we need a global definition
> at this point.

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Michal Simek]

On 09/13/2012 11:28 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +static inline int mdio_wait(struct eth_device *dev)
>> +{
>> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
>> +	u32 timeout = 200;
>> +
>> +	/* Wait till MDIO interface is ready to accept a new transaction. */
>> +	while (timeout && !(readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)) {
>
> I'd say, rework this to
>
> while (--timeout) {
> 	if (readl() & ... )
> 		break;
> 	WATCHDOG_RESET();
> }
>
> The WATCHDOG_RESET will give you the udelay and restart the WDT if you use any.
> Also, I think it's more readable when you omit the complex condition for the
> while cycle and split it a bit.

make sense

>
>> +		timeout--;
>> +		udelay(1);
>> +	}
>> +
>> +	if (!timeout) {
>> +		printf("%s: Timeout\n", __func__);
>> +		return 1;
>> +	}
>> +
>> +	return 0;
>> +}
>
> [...]
>
>> +static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
>> +{
>> +	int tmp;
>> +	int i;
>> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
>> +	struct zynq_gem_priv *priv = dev->priv;
>> +	struct phy_device *phydev;
>> +	u32 supported = SUPPORTED_10baseT_Half |
>> +			SUPPORTED_10baseT_Full |
>> +			SUPPORTED_100baseT_Half |
>> +			SUPPORTED_100baseT_Full |
>> +			SUPPORTED_1000baseT_Half |
>> +			SUPPORTED_1000baseT_Full;
>> +
>> +	if (priv->initialized)
>> +		return 0;
>> +
>> +	/* Disable all interrupts */
>> +	writel(0xFFFFFFFF, &regs->idr);
>> +
>> +	/* Disable the receiver & transmitter */
>> +	writel(0, &regs->nwctrl);
>> +	writel(0, &regs->txsr);
>> +	writel(0, &regs->rxsr);
>> +	writel(0, &regs->phymntnc);
>> +
>> +	/* Clear the Hash registers for the mac address pointed by AddressPtr */
>> +	writel(0x0, &regs->hashl);
>> +	/* Write bits [63:32] in TOP */
>> +	writel(0x0, &regs->hashh);
>> +
>> +	/* Clear all counters */
>> +	for (i = 0; i <= (sizeof(struct zynq_gem_regs) -
>> +			offsetof(struct zynq_gem_regs, stat)) / 4; i++)
>
> Add a const int variable and use it here so you don't have to break the for () .

if you like.

>
>> +		readl(&regs->stat[i]);
>> +
>> +	/* Setup RxBD space */
>> +	memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
>> +	/* Create the RxBD ring */
>> +	memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
>> +
>> +	for (i = 0; i < RX_BUF; i++) {
>> +		priv->rx_bd[i].status = 0xF0000000;
>> +		priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
>> +							(i * PKTSIZE_ALIGN));
>> +	}
>> +	/* WRAP bit to last BD */
>> +	priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
>> +	/* Write RxBDs to IP */
>> +	writel((u32) &(priv->rx_bd), &regs->rxqbase);
>> +
>> +
>> +	/* MAC Setup */
>> +	/*
>> +	 *  Following is the setup for Network Configuration register.
>> +	 *  Bit 0:  Set for 100 Mbps operation.
>> +	 *  Bit 1:  Set for Full Duplex mode.
>> +	 *  Bit 4:  Unset to allow Copy all frames - MAC checking
>> +	 *  Bit 17: Set for FCS removal.
>> +	 *  Bits 20-18: Set with value binary 010 to divide pclk by 32
>> +	 *              (pclk up to 80 MHz)
>> +	 */
>> +	writel(0x000A0003, &regs->nwcfg);
>
> Well you know ... magic numbers and defined bits ;-)


:-) Or. let me create macros.


>
>> +	/*
>> +	 * Following is the setup for DMA Configuration register.
>> +	 * Bits 4-0: To set AHB fixed burst length for DMA data operations ->
>> +	 *  Set with binary 00100 to use INCR4 AHB bursts.
>> +	 * Bits 9-8: Receiver packet buffer memory size ->
>> +	 *  Set with binary 11 to Use full configured addressable space (8 Kb)
>> +	 * Bit 10  : Transmitter packet buffer memory size ->
>> +	 *  Set with binary 1 to Use full configured addressable space (4 Kb)
>> +	 * Bits 23-16 : DMA receive buffer size in AHB system memory ->
>> +	 *  Set with binary 00011000 to use 1536 byte(1*max length frame/buffer)
>> +	 */
>> +	writel(0x00180704, &regs->dmacr);

the same here.

>> +
>> +	/*
>> +	 * Following is the setup for Network Control register.
>> +	 * Bit 2:  Set to enable Receive operation.
>> +	 * Bit 3:  Set to enable Transmitt operation.
>> +	 * Bit 4:  Set to enable MDIO operation.
>> +	 */
>> +	tmp = readl(&regs->nwctrl);
>> +	/* MDIO, Rx and Tx enable */
>> +	tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
>> +	    ZYNQ_GEM_NWCTRL_TXEN_MASK;
>> +	writel(tmp, &regs->nwctrl);
>
> setbits_le32()

ok.

>
>> +	/* interface - look at tsec */
>> +	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
>> +
>> +	phydev->supported &= supported;
>> +	phydev->advertising = phydev->supported;
>> +	priv->phydev = phydev;
>> +	phy_config(phydev);
>> +	phy_startup(phydev);
>> +
>> +	priv->initialized = 1;
>> +	return 0;
>> +}
>> +
>> +static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
>> +{
>> +	int status;
>> +	u32 val;
>> +	struct zynq_gem_priv *priv = dev->priv;
>> +	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
>> +
>> +	if (!priv->initialized) {
>> +		puts("Error GMAC not initialized");
>> +		return -1;
>> +	}
>> +
>> +	/* setup BD */
>> +	writel((u32)&(priv->tx_bd), &regs->txqbase);
>> +
>> +	/* Setup Tx BD */
>> +	memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd));
>> +
>> +	priv->tx_bd.addr = (u32)ptr;
>> +	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK |
>> +						ZYNQ_GEM_TXBUF_WRAP_MASK;
>> +
>> +	/* Start transmit */
>> +	val = readl(&regs->nwctrl) | ZYNQ_GEM_NWCTRL_STARTTX_MASK;
>> +	writel(val, &regs->nwctrl);
>
> setbits_le32()

ok

>
>> +	/* Read the stat register to know if the packet has been transmitted */
>> +	status = readl(&regs->txsr);
>> +	if (status & (ZYNQ_GEM_TXSR_HRESPNOK_MASK | ZYNQ_GEM_TXSR_URUN_MASK |
>> +						ZYNQ_GEM_TXSR_BUFEXH_MASK)) {
>
> Add const int mask for the above.

or macro should be fine.


>
>> +		printf("Something has gone wrong here!? Status is 0x%x.\n",
>> +		       status);
>> +	}
>> +
>> +	/* Clear Tx status register before leaving . */
>> +	writel(status, &regs->txsr);
>> +	return 0;
>> +}
>> +
>> +/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD
>> */ +static int zynq_gem_recv(struct eth_device *dev)
>> +{
>> +	int frame_len;
>> +	struct zynq_gem_priv *priv = dev->priv;
>> +
>> +	if (!(priv->rx_bd[priv->rxbd_current].addr & ZYNQ_GEM_RXBUF_NEW_MASK))
>> +		return 0;
>> +
>> +	if (!(priv->rx_bd[priv->rxbd_current].status &
>> +			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
>> +		printf("GEM: SOF or EOF not set for last buffer received!\n");
>> +		return 0;
>> +	}
>> +
>> +	frame_len = priv->rx_bd[priv->rxbd_current].status &
>> +							ZYNQ_GEM_RXBUF_LEN_MASK;
>
> Just introduce some variable for priv->rx_bd[priv->rxbd_current] so you don't
> have such long lines

no problem.

>
>> +	if (frame_len) {
>> +		NetReceive((u8 *) (priv->rx_bd[priv->rxbd_current].addr &
>> +					ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
>> +
>> +		if (priv->rx_bd[priv->rxbd_current].status &
>> +							ZYNQ_GEM_RXBUF_SOF_MASK)
>> +			priv->rx_first_buf = priv->rxbd_current;
>> +		else {
>> +			priv->rx_bd[priv->rxbd_current].addr &=
>> +						~ZYNQ_GEM_RXBUF_NEW_MASK;
>> +			priv->rx_bd[priv->rxbd_current].status = 0xF0000000;
>> +		}
>> +
>> +		if (priv->rx_bd[priv->rxbd_current].status &
>> +						ZYNQ_GEM_RXBUF_EOF_MASK) {
>> +			priv->rx_bd[priv->rx_first_buf].addr &=
>> +						~ZYNQ_GEM_RXBUF_NEW_MASK;
>> +			priv->rx_bd[priv->rx_first_buf].status = 0xF0000000;
>> +		}
>> +
>> +		if ((++priv->rxbd_current) >= RX_BUF)
>> +			priv->rxbd_current = 0;
>> +
>> +		return frame_len;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void zynq_gem_halt(struct eth_device *dev)
>> +{
>> +	return;
>
> Does this need to be implemented at all ?

probably not.
Let me do that changes and I will send updated version.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Marek Vasut]

Dear Michal Simek,

[...]

> > 
> > Add const int mask for the above.
> 
> or macro should be fine.

const int is better due to type checking .

[...]

Thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Joe Hershberger]

Hi Marek,

On Thu, Sep 13, 2012 at 4:28 AM, Marek Vasut <marex@denx.de> wrote:
> Dear Michal Simek,
>> +     /*
>> +      * Following is the setup for Network Control register.
>> +      * Bit 2:  Set to enable Receive operation.
>> +      * Bit 3:  Set to enable Transmitt operation.
>> +      * Bit 4:  Set to enable MDIO operation.
>> +      */
>> +     tmp = readl(&regs->nwctrl);
>> +     /* MDIO, Rx and Tx enable */
>> +     tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
>> +         ZYNQ_GEM_NWCTRL_TXEN_MASK;
>> +     writel(tmp, &regs->nwctrl);
>
> setbits_le32()

This is not equivalent.  Using setbits_le32() will not provide a dmb()
on the operations the way that readl(), writel() does.  I believe this
will cause problems when the dcache is enabled, right?

-Joe

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Marek Vasut]

Dear Joe Hershberger,

> Hi Marek,
> 
> On Thu, Sep 13, 2012 at 4:28 AM, Marek Vasut <marex@denx.de> wrote:
> > Dear Michal Simek,
> > 
> >> +     /*
> >> +      * Following is the setup for Network Control register.
> >> +      * Bit 2:  Set to enable Receive operation.
> >> +      * Bit 3:  Set to enable Transmitt operation.
> >> +      * Bit 4:  Set to enable MDIO operation.
> >> +      */
> >> +     tmp = readl(&regs->nwctrl);
> >> +     /* MDIO, Rx and Tx enable */
> >> +     tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
> >> +         ZYNQ_GEM_NWCTRL_TXEN_MASK;
> >> +     writel(tmp, &regs->nwctrl);
> > 
> > setbits_le32()
> 
> This is not equivalent.  Using setbits_le32() will not provide a dmb()
> on the operations the way that readl(), writel() does.  I believe this
> will cause problems when the dcache is enabled, right?

Not when dcache is enabled, the register space isn't cached. But the compiler 
can run some wild optimizations across that. So where's the problem, do we add 
dmb() to clrsetbits() calls ?

> -Joe

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Marek Vasut]

Dear Joe Hershberger,

> On Thu, Sep 13, 2012 at 11:45 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Joe Hershberger,
> > 
> >> Hi Marek,
> >> 
> >> On Thu, Sep 13, 2012 at 4:28 AM, Marek Vasut <marex@denx.de> wrote:
> >> > Dear Michal Simek,
> >> > 
> >> >> +     /*
> >> >> +      * Following is the setup for Network Control register.
> >> >> +      * Bit 2:  Set to enable Receive operation.
> >> >> +      * Bit 3:  Set to enable Transmitt operation.
> >> >> +      * Bit 4:  Set to enable MDIO operation.
> >> >> +      */
> >> >> +     tmp = readl(&regs->nwctrl);
> >> >> +     /* MDIO, Rx and Tx enable */
> >> >> +     tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
> >> >> +         ZYNQ_GEM_NWCTRL_TXEN_MASK;
> >> >> +     writel(tmp, &regs->nwctrl);
> >> > 
> >> > setbits_le32()
> >> 
> >> This is not equivalent.  Using setbits_le32() will not provide a dmb()
> >> on the operations the way that readl(), writel() does.  I believe this
> >> will cause problems when the dcache is enabled, right?
> > 
> > Not when dcache is enabled, the register space isn't cached. But the
> > compiler can run some wild optimizations across that. So where's the
> > problem, do we add dmb() to clrsetbits() calls ?
> 
> I'm not grokking this paragraph.

The only thing that is ever cached is DRAM. It's the only cacheable area 
configured in the MMU tables. The rest is uncached.

And the dmb() doesn't have anything to do with caches, it has to do with 
compiler reordering the register accesses, which might screw things up.

But wait, I shouldn't reply to emails when I've been awake for 20+ hours. Look 
at the macro again. Let's see an example:

clrbits_le32 expands to clrbits(le32, ...)
clrbits(le32, ...) expands to out_le32(..., in_le32(...) & ~...)

out_le32() expands to out_arch() which expands to __raw_writel()
in_le32() expands to in_arch() which expands to __raw_readl()

__raw_writel() expands to __arch_putl()
__raw_readl() expands to __arch_getl()

arch_putl() is *(volatile unsigned long *), therefore compiler reordering 
doesn't happen accross this (because of the volatile). So is arch_getl() .

Bottom line, no need for explicit dmb() in clrsetbits_le32() and friends. But 
whew, you got me scared there ;-)

> You are saying that when the dcache is enabled, that the register
> space is not cached?  Why would it not be?  It doesn't know those
> addresses from any other memory, right?
> 
> clrsetbits() does not call dmb().  Perhaps it should.  It's never been
> clear to me why writeX/readX used dmb, but out_XY/in_XY/clrsetbits_XY
> do not.  Are they not both for accessing registers?
> 
> Perhaps test all of these drivers with write-back cache enabled and
> make sure they work.
> 
> -Joe

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

Add timer driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Move lowlevel_init.S from board to cpu folder
    Remove XPSS prefix
    Rename XSCUTIMER -> SCUTIMER

Keep timer in zynq folder till ARM custodian comments it.
---
 arch/arm/cpu/armv7/zynq/Makefile        |   52 +++++++++++
 arch/arm/cpu/armv7/zynq/lowlevel_init.S |   27 ++++++
 arch/arm/cpu/armv7/zynq/timer.c         |  151 +++++++++++++++++++++++++++++++
 3 files changed, 230 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
 create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/zynq/timer.c

diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 0000000..1d2d7e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS-y	:= lowlevel_init.o
+COBJS-y	:= timer.o
+
+SOBJS	:= $(SOBJS-y)
+COBJS	:= $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/cpu/armv7/zynq/lowlevel_init.S
new file mode 100644
index 0000000..642eb18
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+        mov     pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 0000000..0252220
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+	u32 load; /* Timer Load Register */
+	u32 counter; /* Timer Counter Register */
+	u32 control; /* Timer Control Register */
+};
+
+static struct scu_timer *timer_base = CONFIG_SCUTIMER_BASEADDR;
+
+#define SCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /* Prescaler */
+#define SCUTIMER_CONTROL_PRESCALER_SHIFT	8
+#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002 /* Auto-reload */
+#define SCUTIMER_CONTROL_ENABLE_MASK		0x00000001 /* Timer enable */
+
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+#define TIMER_PRESCALE 255
+#define TIMER_TICK_HZ  (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
+
+int timer_init(void)
+{
+	u32 val;
+
+	/* Load the timer counter register */
+	writel(0xFFFFFFFF, &timer_base->counter);
+
+	/* Start the A9Timer device */
+	val = readl(&timer_base->control);
+	/* Enable Auto reload mode */
+	val |= SCUTIMER_CONTROL_AUTO_RELOAD_MASK;
+	/* Clear prescaler control bits */
+	val &= ~SCUTIMER_CONTROL_PRESCALER_MASK;
+	/* Set prescaler value */
+	val |= (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT);
+	/* Enable the decrementer */
+	val |= SCUTIMER_CONTROL_ENABLE_MASK;
+	writel(val, &timer_base->control);
+
+	/* Reset time */
+	gd->lastinc = readl(&timer_base->counter) /
+					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
+	gd->tbl = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+ulong get_timer_masked(void)
+{
+	ulong now;
+
+	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+
+	if (gd->lastinc >= now) {
+		/* Normal mode */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* We have an overflow ... */
+		gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+	}
+	gd->lastinc = now;
+
+	return gd->tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec / (1000000 / CONFIG_SYS_HZ);
+	tmp = get_ticks() + tmo; /* Get current timestamp */
+
+	while (get_ticks() < tmp) { /* Loop till event */
+		 /* NOP */;
+	}
+}
+
+/* Timer without interrupts */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
-- 
1.7.0.4

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

On 08/16/2012 08:30 AM, Michal Simek wrote:
> Add timer driver.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Move lowlevel_init.S from board to cpu folder
>      Remove XPSS prefix
>      Rename XSCUTIMER -> SCUTIMER
>
> Keep timer in zynq folder till ARM custodian comments it.
> ---
>   arch/arm/cpu/armv7/zynq/Makefile        |   52 +++++++++++
>   arch/arm/cpu/armv7/zynq/lowlevel_init.S |   27 ++++++
>   arch/arm/cpu/armv7/zynq/timer.c         |  151 +++++++++++++++++++++++++++++++
>   3 files changed, 230 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
>   create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S
>   create mode 100644 arch/arm/cpu/armv7/zynq/timer.c

We haven't got any reaction for Albert.
Marek and Joe: Can you review this? And give me your ACK or NACK.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Marek Vasut]

Dear Michal Simek,

> On 08/16/2012 08:30 AM, Michal Simek wrote:
> > Add timer driver.
> > 
> > Signed-off-by: Michal Simek <monstr@monstr.eu>
> > 
> > ---
> > v2: Move lowlevel_init.S from board to cpu folder
> > 
> >      Remove XPSS prefix
> >      Rename XSCUTIMER -> SCUTIMER
> > 
> > Keep timer in zynq folder till ARM custodian comments it.
> > ---
> > 
> >   arch/arm/cpu/armv7/zynq/Makefile        |   52 +++++++++++
> >   arch/arm/cpu/armv7/zynq/lowlevel_init.S |   27 ++++++
> >   arch/arm/cpu/armv7/zynq/timer.c         |  151
> >   +++++++++++++++++++++++++++++++ 3 files changed, 230 insertions(+), 0
> >   deletions(-)
> >   create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
> >   create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S
> >   create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
> 
> We haven't got any reaction for Albert.
> Marek and Joe: Can you review this? And give me your ACK or NACK.

Oh I'll gladly torture you :-)

btw I might need a bit of a review for a ublaze stuff eventually and maybe some 
xilinx uart too, there's a large stdio patchset I have queued. Would you review 
please?

> Thanks,
> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

On 09/13/2012 11:32 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
>> On 08/16/2012 08:30 AM, Michal Simek wrote:
>>> Add timer driver.
>>>
>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>>>
>>> ---
>>> v2: Move lowlevel_init.S from board to cpu folder
>>>
>>>       Remove XPSS prefix
>>>       Rename XSCUTIMER -> SCUTIMER
>>>
>>> Keep timer in zynq folder till ARM custodian comments it.
>>> ---
>>>
>>>    arch/arm/cpu/armv7/zynq/Makefile        |   52 +++++++++++
>>>    arch/arm/cpu/armv7/zynq/lowlevel_init.S |   27 ++++++
>>>    arch/arm/cpu/armv7/zynq/timer.c         |  151
>>>    +++++++++++++++++++++++++++++++ 3 files changed, 230 insertions(+), 0
>>>    deletions(-)
>>>    create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
>>>    create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S
>>>    create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
>>
>> We haven't got any reaction for Albert.
>> Marek and Joe: Can you review this? And give me your ACK or NACK.
>
> Oh I'll gladly torture you :-)

Go ahead. :-)

>
> btw I might need a bit of a review for a ublaze stuff eventually and maybe some
> xilinx uart too, there's a large stdio patchset I have queued. Would you review
> please?

Feel free to contact me if you need any help with any xilinx stuff. Microblaze/xilinx ppc
or current arm code.
I am keen to change current code to u-boot new standard and also with dts support.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Marek Vasut]

Dear Michal Simek,

[...]

> +#include <config.h>
> +#include <linux/linkage.h>
> +
> +ENTRY(lowlevel_init)
> +        mov     pc, lr
> +ENDPROC(lowlevel_init)

inline void lowlevel_init(void) {} works as well and you don't need the assembly 
file.

> diff --git a/arch/arm/cpu/armv7/zynq/timer.c
> b/arch/arm/cpu/armv7/zynq/timer.c new file mode 100644
> index 0000000..0252220
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/zynq/timer.c
> @@ -0,0 +1,151 @@
> +/*
> + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
> + *
> + * (C) Copyright 2008
> + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
> + *
> + * (C) Copyright 2004
> + * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
> + *
> + * (C) Copyright 2002-2004
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * (C) Copyright 2003
> + * Texas Instruments <www.ti.com>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Alex Zuepke <azu@sysgo.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <div64.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct scu_timer {
> +	u32 load; /* Timer Load Register */
> +	u32 counter; /* Timer Counter Register */
> +	u32 control; /* Timer Control Register */
> +};
> +
> +static struct scu_timer *timer_base = CONFIG_SCUTIMER_BASEADDR;
> +
> +#define SCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /* Prescaler */
> +#define SCUTIMER_CONTROL_PRESCALER_SHIFT	8
> +#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002 /* Auto-reload */
> +#define SCUTIMER_CONTROL_ENABLE_MASK		0x00000001 /* Timer enable */
> +
> +#define TIMER_LOAD_VAL 0xFFFFFFFF
> +#define TIMER_PRESCALE 255
> +#define TIMER_TICK_HZ  (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
> +
> +int timer_init(void)
> +{
> +	u32 val;
> +
> +	/* Load the timer counter register */
> +	writel(0xFFFFFFFF, &timer_base->counter);
> +
> +	/* Start the A9Timer device */
> +	val = readl(&timer_base->control);
> +	/* Enable Auto reload mode */
> +	val |= SCUTIMER_CONTROL_AUTO_RELOAD_MASK;
> +	/* Clear prescaler control bits */
> +	val &= ~SCUTIMER_CONTROL_PRESCALER_MASK;
> +	/* Set prescaler value */
> +	val |= (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT);
> +	/* Enable the decrementer */
> +	val |= SCUTIMER_CONTROL_ENABLE_MASK;
> +	writel(val, &timer_base->control);

clrsetbits_le32()

> +	/* Reset time */
> +	gd->lastinc = readl(&timer_base->counter) /
> +					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
> +	gd->tbl = 0;
> +
> +	return 0;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long
> long). + * On ARM it just returns the timer value.
> + */
> +ulong get_timer_masked(void)
> +{
> +	ulong now;
> +
> +	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
> +
> +	if (gd->lastinc >= now) {
> +		/* Normal mode */
> +		gd->tbl += gd->lastinc - now;
> +	} else {
> +		/* We have an overflow ... */
> +		gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
> +	}
> +	gd->lastinc = now;
> +
> +	return gd->tbl;
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> +	unsigned long long tmp;
> +	ulong tmo;
> +
> +	tmo = usec / (1000000 / CONFIG_SYS_HZ);
> +	tmp = get_ticks() + tmo; /* Get current timestamp */
> +
> +	while (get_ticks() < tmp) { /* Loop till event */
> +		 /* NOP */;
> +	}
> +}
> +
> +/* Timer without interrupts */
> +ulong get_timer(ulong base)
> +{
> +	return get_timer_masked() - base;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long
> long). + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> +	return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> +	return CONFIG_SYS_HZ;
> +}

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

On 09/13/2012 11:31 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +#include <config.h>
>> +#include <linux/linkage.h>
>> +
>> +ENTRY(lowlevel_init)
>> +        mov     pc, lr
>> +ENDPROC(lowlevel_init)
>
> inline void lowlevel_init(void) {} works as well and you don't need the assembly
> file.

:-) yes. The reason why I have done it in this way that we have some asm code
which will go to this area. That's why I have kept it in asm instead of C.

Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 11:31 AM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> > [...]
> > 
> >> +#include <config.h>
> >> +#include <linux/linkage.h>
> >> +
> >> +ENTRY(lowlevel_init)
> >> +        mov     pc, lr
> >> +ENDPROC(lowlevel_init)
> > 
> > inline void lowlevel_init(void) {} works as well and you don't need the
> > assembly file.
> :
> :-) yes. The reason why I have done it in this way that we have some asm
> :code
> 
> which will go to this area. That's why I have kept it in asm instead of C.

What code? Will the code go into lowlevel_init() ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

On 09/13/2012 12:31 PM, Marek Vasut wrote:
> Dear Michal Simek,
>
>> On 09/13/2012 11:31 AM, Marek Vasut wrote:
>>> Dear Michal Simek,
>>>
>>> [...]
>>>
>>>> +#include <config.h>
>>>> +#include <linux/linkage.h>
>>>> +
>>>> +ENTRY(lowlevel_init)
>>>> +        mov     pc, lr
>>>> +ENDPROC(lowlevel_init)
>>>
>>> inline void lowlevel_init(void) {} works as well and you don't need the
>>> assembly file.
>> :
>> :-) yes. The reason why I have done it in this way that we have some asm
>> :code
>>
>> which will go to this area. That's why I have kept it in asm instead of C.
>
> What code? Will the code go into lowlevel_init() ?

For example SLCR locking if is not locked from the first stage bootloader.
Also if necessary OCM and DDR remap, FPGA reset can be also there
based on configuration.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 12:31 PM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> >> On 09/13/2012 11:31 AM, Marek Vasut wrote:
> >>> Dear Michal Simek,
> >>> 
> >>> [...]
> >>> 
> >>>> +#include <config.h>
> >>>> +#include <linux/linkage.h>
> >>>> +
> >>>> +ENTRY(lowlevel_init)
> >>>> +        mov     pc, lr
> >>>> +ENDPROC(lowlevel_init)
> >>> 
> >>> inline void lowlevel_init(void) {} works as well and you don't need the
> >>> assembly file.
> >>> 
> >> :-) yes. The reason why I have done it in this way that we have some asm
> >> :code
> >> 
> >> which will go to this area. That's why I have kept it in asm instead of
> >> C.
> > 
> > What code? Will the code go into lowlevel_init() ?
> 
> For example SLCR locking if is not locked from the first stage bootloader.
> Also if necessary OCM and DDR remap, FPGA reset can be also there
> based on configuration.

Can it not be in C code ?

> Thanks,
> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Michal Simek]

On 09/13/2012 02:32 PM, Marek Vasut wrote:
> Dear Michal Simek,
>
>> On 09/13/2012 12:31 PM, Marek Vasut wrote:
>>> Dear Michal Simek,
>>>
>>>> On 09/13/2012 11:31 AM, Marek Vasut wrote:
>>>>> Dear Michal Simek,
>>>>>
>>>>> [...]
>>>>>
>>>>>> +#include <config.h>
>>>>>> +#include <linux/linkage.h>
>>>>>> +
>>>>>> +ENTRY(lowlevel_init)
>>>>>> +        mov     pc, lr
>>>>>> +ENDPROC(lowlevel_init)
>>>>>
>>>>> inline void lowlevel_init(void) {} works as well and you don't need the
>>>>> assembly file.
>>>>>
>>>> :-) yes. The reason why I have done it in this way that we have some asm
>>>> :code
>>>>
>>>> which will go to this area. That's why I have kept it in asm instead of
>>>> C.
>>>
>>> What code? Will the code go into lowlevel_init() ?
>>
>> For example SLCR locking if is not locked from the first stage bootloader.
>> Also if necessary OCM and DDR remap, FPGA reset can be also there
>> based on configuration.
>
> Can it not be in C code ?

Probably can be in C code. I have no problem to move it to C.

Cheers,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 02:32 PM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> >> On 09/13/2012 12:31 PM, Marek Vasut wrote:
> >>> Dear Michal Simek,
> >>> 
> >>>> On 09/13/2012 11:31 AM, Marek Vasut wrote:
> >>>>> Dear Michal Simek,
> >>>>> 
> >>>>> [...]
> >>>>> 
> >>>>>> +#include <config.h>
> >>>>>> +#include <linux/linkage.h>
> >>>>>> +
> >>>>>> +ENTRY(lowlevel_init)
> >>>>>> +        mov     pc, lr
> >>>>>> +ENDPROC(lowlevel_init)
> >>>>> 
> >>>>> inline void lowlevel_init(void) {} works as well and you don't need
> >>>>> the assembly file.
> >>>>> 
> >>>> :-) yes. The reason why I have done it in this way that we have some
> >>>> :asm code
> >>>> 
> >>>> which will go to this area. That's why I have kept it in asm instead
> >>>> of C.
> >>> 
> >>> What code? Will the code go into lowlevel_init() ?
> >> 
> >> For example SLCR locking if is not locked from the first stage
> >> bootloader. Also if necessary OCM and DDR remap, FPGA reset can be also
> >> there based on configuration.
> > 
> > Can it not be in C code ?
> 
> Probably can be in C code. I have no problem to move it to C.

Please do, cut the assembly to minimum.

> Cheers,
> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Michal Simek]

Add support for Xilinx Zynq board.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Forget to also add config file

v3: Change name for serial driver
    Remove lowlevel_init from board folder
    Remove XPSS part from timer baseaddr
    Change name for Zynq gem driver
    Clean coding style
    Remove mac + ip addresses from config file
    Remove additional PHYs
---
 board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
 board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
 boards.cfg                 |    1 +
 include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 229 insertions(+), 0 deletions(-)
 create mode 100644 board/xilinx/zynq/Makefile
 create mode 100644 board/xilinx/zynq/board.c
 create mode 100644 include/configs/zynq.h

diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 0000000..ef4faa1
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= board.o
+
+COBJS	:= $(sort $(COBJS-y))
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 0000000..4cb36f6
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#endif
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	while (1)
+		;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..aeca912 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+zynq                         arm         armv7       zynq                xilinx         zynq
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
new file mode 100644
index 0000000..8fb4f1b
--- /dev/null
+++ b/include/configs/zynq.h
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ZYNQ_H
+#define __CONFIG_ZYNQ_H
+
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_ZYNQ
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ	800000000
+#define CONFIG_SYS_HZ		1000
+
+/* Ram */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_BAUDRATE		115200
+
+/* XPSS Serial driver */
+#define CONFIG_ZYNQ_SERIAL
+#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
+#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
+#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
+
+/* SCU timer address is hardcoded */
+#define CONFIG_SCUTIMER_BASEADDR	0xF8F00600
+
+/* Ethernet driver */
+#define CONFIG_NET_MULTI
+#define CONFIG_ZYNQ_GEM
+#define CONFIG_ZYNQ_GEM_BASEADDR0	0xE000B000
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* MII and Phylib */
+#define CONFIG_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x10000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MALLOC_LEN		0x400000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_LOAD_ADDR	0
+#define CONFIG_SYS_MAXARGS	15 /* max number of command args */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* OF */
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#endif /* __CONFIG_ZYNQ_H */
-- 
1.7.0.4

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Michal Simek]

On 08/16/2012 08:30 AM, Michal Simek wrote:
> Add support for Xilinx Zynq board.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Forget to also add config file
>
> v3: Change name for serial driver
>      Remove lowlevel_init from board folder
>      Remove XPSS part from timer baseaddr
>      Change name for Zynq gem driver
>      Clean coding style
>      Remove mac + ip addresses from config file
>      Remove additional PHYs
> ---
>   board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>   board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>   boards.cfg                 |    1 +
>   include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>   4 files changed, 229 insertions(+), 0 deletions(-)
>   create mode 100644 board/xilinx/zynq/Makefile
>   create mode 100644 board/xilinx/zynq/board.c
>   create mode 100644 include/configs/zynq.h
>

The same for this one.
Marek and Joe: Can you please review this?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Marek Vasut]

Dear Michal Simek,

[...]

> +int board_init(void)
> +{
> +	icache_enable();

Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;

You don't need this.

> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int board_eth_init(bd_t *bis)
> +{
> +	int ret = 0;
> +
> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);

ret |= ? ;-)

> +#endif
> +
> +	return ret;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> +	return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +	while (1)
> +		;
> +}

This is definitelly CPU specific.
[...]

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Michal Simek]

On 09/13/2012 11:35 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +int board_init(void)
>> +{
>> +	icache_enable();
>
> Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

Will check this one.

>
>> +	return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +	return 0;
>
> You don't need this.

Will check it too.

>
>> +}
>> +
>> +#ifdef CONFIG_CMD_NET
>> +int board_eth_init(bd_t *bis)
>> +{
>> +	int ret = 0;
>> +
>> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
>> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
>
> ret |= ? ;-)

The reason is that I will wire axi_ethernet and ethernet lite drivers here too.
If this is the problem I can fix it but the next patch will return it
to this style.

>
>> +#endif
>> +
>> +	return ret;
>> +}
>> +#endif
>> +
>> +int dram_init(void)
>> +{
>> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
>> +	return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +	while (1)
>> +		;
>> +}
>
> This is definitelly CPU specific.
> [...]
>
Right, Moving to different folder make sense.

Thanks,
Michal



-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 11:35 AM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> > [...]
> > 
> >> +int board_init(void)
> >> +{
> >> +	icache_enable();
> > 
> > Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?
> 
> Will check this one.
> 
> >> +	return 0;
> >> +}
> >> +
> >> +int board_late_init(void)
> >> +{
> >> +	return 0;
> > 
> > You don't need this.
> 
> Will check it too.
> 
> >> +}
> >> +
> >> +#ifdef CONFIG_CMD_NET
> >> +int board_eth_init(bd_t *bis)
> >> +{
> >> +	int ret = 0;
> >> +
> >> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> >> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
> > 
> > ret |= ? ;-)
> 
> The reason is that I will wire axi_ethernet and ethernet lite drivers here
> too. If this is the problem I can fix it but the next patch will return it
> to this style.

Logical OR on signed type is wrong. Besides, if one fails, you don't want to 
init the others.

> >> +#endif
> >> +
> >> +	return ret;
> >> +}
> >> +#endif
> >> +
> >> +int dram_init(void)
> >> +{
> >> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> >> +	return 0;
> >> +}
> >> +
> >> +void reset_cpu(ulong addr)
> >> +{
> >> +	while (1)
> >> +		;
> >> +}
> > 
> > This is definitelly CPU specific.
> > [...]
> 
> Right, Moving to different folder make sense.

Directory, no wind blows here :p

> Thanks,
> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Michal Simek]

On 09/13/2012 11:35 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +int board_init(void)
>> +{
>> +	icache_enable();
>
> Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

That option is valid just for blackfin.

In arm1176 and s3c44b0v is this done in arch_cpu_init()
but it is not there for armv7

I have seen that several armv7 boards enable it. For example vexpress, highbank, u8500, etc.

>
>> +	return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +	return 0;
>
> You don't need this.

correct.

Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Joe Hershberger]

Hi Michal,

On Thu, Aug 16, 2012 at 1:30 AM, Michal Simek <monstr@monstr.eu> wrote:
> Add support for Xilinx Zynq board.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Forget to also add config file
>
> v3: Change name for serial driver
>     Remove lowlevel_init from board folder
>     Remove XPSS part from timer baseaddr
>     Change name for Zynq gem driver
>     Clean coding style
>     Remove mac + ip addresses from config file
>     Remove additional PHYs
> ---
>  board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>  board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>  boards.cfg                 |    1 +
>  include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 229 insertions(+), 0 deletions(-)
>  create mode 100644 board/xilinx/zynq/Makefile
>  create mode 100644 board/xilinx/zynq/board.c
>  create mode 100644 include/configs/zynq.h
>
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> new file mode 100644
> index 0000000..4cb36f6
> --- /dev/null
> +++ b/board/xilinx/zynq/board.c
> @@ -0,0 +1,64 @@
> +/*
> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> +       icache_enable();
> +
> +       return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +       return 0;
> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int board_eth_init(bd_t *bis)
> +{
> +       int ret = 0;
> +
> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> +       ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
> +#endif
> +
> +       return ret;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> +
> +       return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +       while (1)
> +               ;
> +}

Why not explicitly reset, like Xilinx tree?

void reset_cpu(ulong addr)
{
        /* unlock SLCR */
        writel(XPSS_SLCR_UNLOCK_KEY, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_UNLOCK);
        /* Tickle soft reset bit */
        writel(1, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_PSS_RST_CTRL);

        while (1)
                ;
}


> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> new file mode 100644
> index 0000000..8fb4f1b
> --- /dev/null
> +++ b/include/configs/zynq.h
> @@ -0,0 +1,110 @@
> +/*
> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_ZYNQ_H
> +#define __CONFIG_ZYNQ_H
> +
> +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
> +#define CONFIG_ZYNQ
> +
> +/* CPU clock */
> +#define CONFIG_CPU_FREQ_HZ     800000000
> +#define CONFIG_SYS_HZ          1000
> +
> +/* Ram */
> +#define CONFIG_NR_DRAM_BANKS           1
> +#define CONFIG_SYS_SDRAM_BASE          0
> +#define CONFIG_SYS_SDRAM_SIZE          0x40000000
> +#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_SDRAM_BASE + 0x1000)
> +
> +/* The following table includes the supported baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE  \
> +       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
> +
> +#define CONFIG_BAUDRATE                115200
> +
> +/* XPSS Serial driver */
> +#define CONFIG_ZYNQ_SERIAL
> +#define CONFIG_ZYNQ_SERIAL_BASEADDR0   0xE0001000
> +#define CONFIG_ZYNQ_SERIAL_BAUDRATE0   CONFIG_BAUDRATE
> +#define CONFIG_ZYNQ_SERIAL_CLOCK0      50000000
> +
> +/* SCU timer address is hardcoded */
> +#define CONFIG_SCUTIMER_BASEADDR       0xF8F00600
> +
> +/* Ethernet driver */
> +#define CONFIG_NET_MULTI
> +#define CONFIG_ZYNQ_GEM
> +#define CONFIG_ZYNQ_GEM_BASEADDR0      0xE000B000
> +
> +#define CONFIG_BOOTP_SERVERIP
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +#define CONFIG_BOOTP_MAY_FAIL
> +
> +/* MII and Phylib */
> +#define CONFIG_MII
> +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MARVELL
> +
> +/* Environment */
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x10000
> +
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_SYS_MALLOC_LEN          0x400000
> +#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_MALLOC_LEN
> +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
> +                                               CONFIG_SYS_INIT_RAM_SIZE - \
> +                                               GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_PROMPT      "U-Boot> "
> +#define CONFIG_SYS_CBSIZE      256 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + \
> +                                       sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +#define CONFIG_SYS_LOAD_ADDR   0
> +#define CONFIG_SYS_MAXARGS     15 /* max number of command args */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
> +
> +/* OF */
> +#define CONFIG_FIT
> +#define CONFIG_OF_LIBFDT
> +
> +/* Commands */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +
> +#endif /* __CONFIG_ZYNQ_H */
> --
> 1.7.0.4
>

[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board

[Michal Simek]

On 09/14/2012 06:03 AM, Joe Hershberger wrote:
> Hi Michal,
>
> On Thu, Aug 16, 2012 at 1:30 AM, Michal Simek <monstr@monstr.eu> wrote:
>> Add support for Xilinx Zynq board.
>>
>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>>
>> ---
>> v2: Forget to also add config file
>>
>> v3: Change name for serial driver
>>      Remove lowlevel_init from board folder
>>      Remove XPSS part from timer baseaddr
>>      Change name for Zynq gem driver
>>      Clean coding style
>>      Remove mac + ip addresses from config file
>>      Remove additional PHYs
>> ---
>>   board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>>   board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>>   boards.cfg                 |    1 +
>>   include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>>   4 files changed, 229 insertions(+), 0 deletions(-)
>>   create mode 100644 board/xilinx/zynq/Makefile
>>   create mode 100644 board/xilinx/zynq/board.c
>>   create mode 100644 include/configs/zynq.h
>>
>> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
>> new file mode 100644
>> index 0000000..4cb36f6
>> --- /dev/null
>> +++ b/board/xilinx/zynq/board.c
>> @@ -0,0 +1,64 @@
>> +/*
>> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <netdev.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_init(void)
>> +{
>> +       icache_enable();
>> +
>> +       return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +       return 0;
>> +}
>> +
>> +#ifdef CONFIG_CMD_NET
>> +int board_eth_init(bd_t *bis)
>> +{
>> +       int ret = 0;
>> +
>> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
>> +       ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
>> +#endif
>> +
>> +       return ret;
>> +}
>> +#endif
>> +
>> +int dram_init(void)
>> +{
>> +       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
>> +
>> +       return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +       while (1)
>> +               ;
>> +}
>
> Why not explicitly reset, like Xilinx tree?
>
> void reset_cpu(ulong addr)
> {
>          /* unlock SLCR */
>          writel(XPSS_SLCR_UNLOCK_KEY, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_UNLOCK);
>          /* Tickle soft reset bit */
>          writel(1, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_PSS_RST_CTRL);
>
>          while (1)
>                  ;
> }
>

I haven't started to merge all these features and want to merge minimum platform
and then start to clean drivers and features.
Maybe for slcr make sense to create driver and not just unlock it and use
it for code.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Michal Simek]

On 08/16/2012 08:30 AM, Michal Simek wrote:
> The driver is used on Xilinx Zynq platform.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>      Rename driver name
>      Remove driver description
> ---
>   drivers/serial/Makefile      |    1 +
>   drivers/serial/serial_zynq.c |  200 ++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 201 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/serial/serial_zynq.c

Joe: you have reviewed the first version of this patch.
Can you comment it?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Marek Vasut]

Dear Michal Simek,

> The driver is used on Xilinx Zynq platform.
> 
> Signed-off-by: Michal Simek <monstr@monstr.eu>
> 
> ---
> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>     Rename driver name
>     Remove driver description
> ---
>  drivers/serial/Makefile      |    1 +
>  drivers/serial/serial_zynq.c |  200
> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
> insertions(+), 0 deletions(-)
>  create mode 100644 drivers/serial/serial_zynq.c
[...]

It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away please?

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Michal Simek]

On 09/13/2012 11:21 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
>> The driver is used on Xilinx Zynq platform.
>>
>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>>
>> ---
>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>>      Rename driver name
>>      Remove driver description
>> ---
>>   drivers/serial/Makefile      |    1 +
>>   drivers/serial/serial_zynq.c |  200
>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
>> insertions(+), 0 deletions(-)
>>   create mode 100644 drivers/serial/serial_zynq.c
> [...]
>
> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away please?

Yes, it will add serial_multi in the next patch.
Can you give me your ACK or reviewed-by line? :-)


Maybe you have seen it. I have asked for pulling serial multi for uartlite.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 11:21 AM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> >> The driver is used on Xilinx Zynq platform.
> >> 
> >> Signed-off-by: Michal Simek <monstr@monstr.eu>
> >> 
> >> ---
> >> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
> >> 
> >>      Rename driver name
> >>      Remove driver description
> >> 
> >> ---
> >> 
> >>   drivers/serial/Makefile      |    1 +
> >>   drivers/serial/serial_zynq.c |  200
> >> 
> >> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
> >> insertions(+), 0 deletions(-)
> >> 
> >>   create mode 100644 drivers/serial/serial_zynq.c
> > 
> > [...]
> > 
> > It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away
> > please?
> 
> Yes, it will add serial_multi in the next patch.
> Can you give me your ACK or reviewed-by line? :-)

Just squash them into one patch please.

> Maybe you have seen it. I have asked for pulling serial multi for uartlite.

Pulling ?

> Thanks,
> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Michal Simek]

On 09/13/2012 02:33 PM, Marek Vasut wrote:
> Dear Michal Simek,
>
>> On 09/13/2012 11:21 AM, Marek Vasut wrote:
>>> Dear Michal Simek,
>>>
>>>> The driver is used on Xilinx Zynq platform.
>>>>
>>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>>>>
>>>> ---
>>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>>>>
>>>>       Rename driver name
>>>>       Remove driver description
>>>>
>>>> ---
>>>>
>>>>    drivers/serial/Makefile      |    1 +
>>>>    drivers/serial/serial_zynq.c |  200
>>>>
>>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
>>>> insertions(+), 0 deletions(-)
>>>>
>>>>    create mode 100644 drivers/serial/serial_zynq.c
>>>
>>> [...]
>>>
>>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away
>>> please?
>>
>> Yes, it will add serial_multi in the next patch.
>> Can you give me your ACK or reviewed-by line? :-)
>
> Just squash them into one patch please.

Done.

Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Marek Vasut]

Dear Michal Simek,

> On 09/13/2012 02:33 PM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> >> On 09/13/2012 11:21 AM, Marek Vasut wrote:
> >>> Dear Michal Simek,
> >>> 
> >>>> The driver is used on Xilinx Zynq platform.
> >>>> 
> >>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
> >>>> 
> >>>> ---
> >>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
> >>>> 
> >>>>       Rename driver name
> >>>>       Remove driver description
> >>>> 
> >>>> ---
> >>>> 
> >>>>    drivers/serial/Makefile      |    1 +
> >>>>    drivers/serial/serial_zynq.c |  200
> >>>> 
> >>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
> >>>> insertions(+), 0 deletions(-)
> >>>> 
> >>>>    create mode 100644 drivers/serial/serial_zynq.c
> >>> 
> >>> [...]
> >>> 
> >>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away
> >>> please?
> >> 
> >> Yes, it will add serial_multi in the next patch.
> >> Can you give me your ACK or reviewed-by line? :-)
> > 
> > Just squash them into one patch please.
> 
> Done.

Thanks ... my idea is to switch to serial_multi completely, then rework stdio, 
unify serial on top of it and clean up the whole subsystem. Thanks for helping!

> Michal

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Joe Hershberger]

Hi Marek,

On Thu, Sep 13, 2012 at 9:01 AM, Marek Vasut <marex@denx.de> wrote:
> Dear Michal Simek,
>
>> On 09/13/2012 02:33 PM, Marek Vasut wrote:
>> > Dear Michal Simek,
>> >
>> >> On 09/13/2012 11:21 AM, Marek Vasut wrote:
>> >>> Dear Michal Simek,
>> >>>
>> >>>> The driver is used on Xilinx Zynq platform.
>> >>>>
>> >>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>> >>>>
>> >>>> ---
>> >>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>> >>>>
>> >>>>       Rename driver name
>> >>>>       Remove driver description
>> >>>>
>> >>>> ---
>> >>>>
>> >>>>    drivers/serial/Makefile      |    1 +
>> >>>>    drivers/serial/serial_zynq.c |  200
>> >>>>
>> >>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
>> >>>> insertions(+), 0 deletions(-)
>> >>>>
>> >>>>    create mode 100644 drivers/serial/serial_zynq.c
>> >>>
>> >>> [...]
>> >>>
>> >>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away
>> >>> please?
>> >>
>> >> Yes, it will add serial_multi in the next patch.
>> >> Can you give me your ACK or reviewed-by line? :-)
>> >
>> > Just squash them into one patch please.
>>
>> Done.
>
> Thanks ... my idea is to switch to serial_multi completely, then rework stdio,
> unify serial on top of it and clean up the whole subsystem. Thanks for helping!

I have a patch that I'll send soon that moves the "nulldev" driver to
the serial driver (if CONFIG_SERIAL_MULTI is defined) so that it is
possible to avoid serial init.  I had the problem that the serial port
on my Zynq product lives in the fabric instead of using the hard-core
ones.  This means that the FPGA neds to be configured first, but since
I'm using u-boot for that too, I need it to start as null and switch
to the fabric serial after the FPGA is configured.  Anyway, just more
support for supporting CONFIG_SERIAL_MULTI.

-Joe

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Marek Vasut]

Dear Joe Hershberger,

> Hi Marek,
> 
> On Thu, Sep 13, 2012 at 9:01 AM, Marek Vasut <marex@denx.de> wrote:
> > Dear Michal Simek,
> > 
> >> On 09/13/2012 02:33 PM, Marek Vasut wrote:
> >> > Dear Michal Simek,
> >> > 
> >> >> On 09/13/2012 11:21 AM, Marek Vasut wrote:
> >> >>> Dear Michal Simek,
> >> >>> 
> >> >>>> The driver is used on Xilinx Zynq platform.
> >> >>>> 
> >> >>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
> >> >>>> 
> >> >>>> ---
> >> >>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
> >> >>>> 
> >> >>>>       Rename driver name
> >> >>>>       Remove driver description
> >> >>>> 
> >> >>>> ---
> >> >>>> 
> >> >>>>    drivers/serial/Makefile      |    1 +
> >> >>>>    drivers/serial/serial_zynq.c |  200
> >> >>>> 
> >> >>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
> >> >>>> insertions(+), 0 deletions(-)
> >> >>>> 
> >> >>>>    create mode 100644 drivers/serial/serial_zynq.c
> >> >>> 
> >> >>> [...]
> >> >>> 
> >> >>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right
> >> >>> away please?
> >> >> 
> >> >> Yes, it will add serial_multi in the next patch.
> >> >> Can you give me your ACK or reviewed-by line? :-)
> >> > 
> >> > Just squash them into one patch please.
> >> 
> >> Done.
> > 
> > Thanks ... my idea is to switch to serial_multi completely, then rework
> > stdio, unify serial on top of it and clean up the whole subsystem.
> > Thanks for helping!
> 
> I have a patch that I'll send soon that moves the "nulldev" driver to
> the serial driver (if CONFIG_SERIAL_MULTI is defined) so that it is
> possible to avoid serial init.

Thanks, this will break my massive patchset though. Can you check 
git://git.denx.de/u-boot-marex.git / stdio branch ? I did something to nulldev 
there. Probably ignore the top 7 patches, they're bogus and need further work. 
It's all still work in progress to some point.

> I had the problem that the serial port
> on my Zynq product lives in the fabric instead of using the hard-core
> ones.

I see ... why don't you implement nulldev_serial instead and leave nulldev stdio 
as is?

> This means that the FPGA neds to be configured first, but since
> I'm using u-boot for that too, I need it to start as null and switch
> to the fabric serial after the FPGA is configured.  Anyway, just more
> support for supporting CONFIG_SERIAL_MULTI.
> 
> -Joe

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Joe Hershberger]

Hi Marek,

On Thu, Sep 13, 2012 at 11:47 PM, Marek Vasut <marex@denx.de> wrote:
> Dear Joe Hershberger,
>
>> Hi Marek,
>>
>> On Thu, Sep 13, 2012 at 9:01 AM, Marek Vasut <marex@denx.de> wrote:
>> > Dear Michal Simek,
>> >
>> >> On 09/13/2012 02:33 PM, Marek Vasut wrote:
>> >> > Dear Michal Simek,
>> >> >
>> >> >> On 09/13/2012 11:21 AM, Marek Vasut wrote:
>> >> >>> Dear Michal Simek,
>> >> >>>
>> >> >>>> The driver is used on Xilinx Zynq platform.
>> >> >>>>
>> >> >>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>> >> >>>>
>> >> >>>> ---
>> >> >>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
>> >> >>>>
>> >> >>>>       Rename driver name
>> >> >>>>       Remove driver description
>> >> >>>>
>> >> >>>> ---
>> >> >>>>
>> >> >>>>    drivers/serial/Makefile      |    1 +
>> >> >>>>    drivers/serial/serial_zynq.c |  200
>> >> >>>>
>> >> >>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
>> >> >>>> insertions(+), 0 deletions(-)
>> >> >>>>
>> >> >>>>    create mode 100644 drivers/serial/serial_zynq.c
>> >> >>>
>> >> >>> [...]
>> >> >>>
>> >> >>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI right
>> >> >>> away please?
>> >> >>
>> >> >> Yes, it will add serial_multi in the next patch.
>> >> >> Can you give me your ACK or reviewed-by line? :-)
>> >> >
>> >> > Just squash them into one patch please.
>> >>
>> >> Done.
>> >
>> > Thanks ... my idea is to switch to serial_multi completely, then rework
>> > stdio, unify serial on top of it and clean up the whole subsystem.
>> > Thanks for helping!
>>
>> I have a patch that I'll send soon that moves the "nulldev" driver to
>> the serial driver (if CONFIG_SERIAL_MULTI is defined) so that it is
>> possible to avoid serial init.
>
> Thanks, this will break my massive patchset though. Can you check
> git://git.denx.de/u-boot-marex.git / stdio branch ? I did something to nulldev
> there. Probably ignore the top 7 patches, they're bogus and need further work.
> It's all still work in progress to some point.

Too bad I can't just browse this at gitweb.

>> I had the problem that the serial port
>> on my Zynq product lives in the fabric instead of using the hard-core
>> ones.
>
> I see ... why don't you implement nulldev_serial instead and leave nulldev stdio
> as is?

Mostly because there is little point in supporting both at the same time.

-Joe

[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver

[Marek Vasut]

Dear Joe Hershberger,

> Hi Marek,
> 
> On Thu, Sep 13, 2012 at 11:47 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Joe Hershberger,
> > 
> >> Hi Marek,
> >> 
> >> On Thu, Sep 13, 2012 at 9:01 AM, Marek Vasut <marex@denx.de> wrote:
> >> > Dear Michal Simek,
> >> > 
> >> >> On 09/13/2012 02:33 PM, Marek Vasut wrote:
> >> >> > Dear Michal Simek,
> >> >> > 
> >> >> >> On 09/13/2012 11:21 AM, Marek Vasut wrote:
> >> >> >>> Dear Michal Simek,
> >> >> >>> 
> >> >> >>>> The driver is used on Xilinx Zynq platform.
> >> >> >>>> 
> >> >> >>>> Signed-off-by: Michal Simek <monstr@monstr.eu>
> >> >> >>>> 
> >> >> >>>> ---
> >> >> >>>> v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
> >> >> >>>> 
> >> >> >>>>       Rename driver name
> >> >> >>>>       Remove driver description
> >> >> >>>> 
> >> >> >>>> ---
> >> >> >>>> 
> >> >> >>>>    drivers/serial/Makefile      |    1 +
> >> >> >>>>    drivers/serial/serial_zynq.c |  200
> >> >> >>>> 
> >> >> >>>> ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201
> >> >> >>>> insertions(+), 0 deletions(-)
> >> >> >>>> 
> >> >> >>>>    create mode 100644 drivers/serial/serial_zynq.c
> >> >> >>> 
> >> >> >>> [...]
> >> >> >>> 
> >> >> >>> It looks ok, but can you make it support CONFIG_SERIAL_MULTI
> >> >> >>> right away please?
> >> >> >> 
> >> >> >> Yes, it will add serial_multi in the next patch.
> >> >> >> Can you give me your ACK or reviewed-by line? :-)
> >> >> > 
> >> >> > Just squash them into one patch please.
> >> >> 
> >> >> Done.
> >> > 
> >> > Thanks ... my idea is to switch to serial_multi completely, then
> >> > rework stdio, unify serial on top of it and clean up the whole
> >> > subsystem. Thanks for helping!
> >> 
> >> I have a patch that I'll send soon that moves the "nulldev" driver to
> >> the serial driver (if CONFIG_SERIAL_MULTI is defined) so that it is
> >> possible to avoid serial init.
> > 
> > Thanks, this will break my massive patchset though. Can you check
> > git://git.denx.de/u-boot-marex.git / stdio branch ? I did something to
> > nulldev there. Probably ignore the top 7 patches, they're bogus and need
> > further work. It's all still work in progress to some point.
> 
> Too bad I can't just browse this at gitweb.

Intended ... just

git remote add marex git://...
git fetch marex
git checkout -t -b stdio marex/stdio

And enjoy the horror show :-)

> >> I had the problem that the serial port
> >> on my Zynq product lives in the fabric instead of using the hard-core
> >> ones.
> > 
> > I see ... why don't you implement nulldev_serial instead and leave
> > nulldev stdio as is?
> 
> Mostly because there is little point in supporting both at the same time.

Can you enlighten me ? stdio != serial, the purpose is different really.

If someone wants to setenv stdout serial and have serial null, be my guest. But 
then there really should be a direct, explicit stdio nulldev too.

> -Joe

Best regards,
Marek Vasut