From: Thierry Reding <thierry.reding@avionic-design.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Cache alignment warnings on Tegra (ARM)
Date: Sat, 15 Sep 2012 22:01:47 +0200 [thread overview]
Message-ID: <20120915200147.GA1900@avionic-0098.mockup.avionic-design.de> (raw)
In-Reply-To: <CAPnjgZ1L0cHaBU+A1JVHAz7DapUqaD3-UFRqoz1sy6_QS7M6iA@mail.gmail.com>
On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> Hi,
>
> On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Stephen Warren,
> >
> >> On 09/12/2012 04:38 PM, Marek Vasut wrote:
> >> > Dear Stephen Warren,
> >> >
> >> >> On 09/12/2012 10:19 AM, Tom Warren wrote:
> >> >>> Folks,
> >> >>>
> >> >>> Stephen Warren has posted an internal bug regarding the cache
> >> >>> alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
> >> >>> the gist:
> >> >>>
> >> >>> Executing "mmc dev 0" still yields cache warnings:
> >> >>>
> >> >>> Tegra20 (Harmony) # mmc dev 0
> >> >>> ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908
> >> >>> mmc0 is current device
> >> >>
> >> >> ...
> >> >>
> >> >>> There have been patches in the past (IIRC) that have tried to ensure
> >> >>> all callers (FS, MMC driver, USB driver, etc.) force their buffers to
> >> >>> the appropriate alignment, but I don't know that we can ever correct
> >> >>> every instance, now or in the future.
> >> >>>
> >> >>> Can we start a discussion about what we can do about this warning?
> >> >>> Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS,
> >> >>> etc.) where Stephen put his #if 0's would be one approach, or changing
> >> >>> the printf() to a debug(), perhaps. As far as I can tell, these
> >> >>> alignment 'errors' don't seem to produce bad data in the transfer.
> >> >>
> >> >> I don't think simply turning off the warning is the correct approach; I
> >> >> believe they represent real problems that can in fact cause data
> >> >> corruption. I don't believe we have any choice other than to fully solve
> >> >> the root-cause.
>
> Yes I agree, and I think it is pretty close - certainly much better
> than it used to be. The good thing about them being annoying is that
> they will likely get fixed :-)
I think I traced this to the copying of CSD a while back. The problem is
that the transferred buffer is 8 bytes, so there's no way to make it
aligned properly. Unfortunately the entailing discussion did not yield a
solution at the time.
Thierry
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next prev parent reply other threads:[~2012-09-15 20:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 16:19 [U-Boot] Cache alignment warnings on Tegra (ARM) Tom Warren
2012-09-12 16:49 ` Stephen Warren
2012-09-12 22:38 ` Marek Vasut
2012-09-12 23:10 ` Stephen Warren
2012-09-12 23:42 ` Marek Vasut
2012-09-14 15:53 ` Simon Glass
2012-09-15 20:01 ` Thierry Reding [this message]
2012-09-15 20:11 ` Marek Vasut
2012-09-15 20:41 ` Thierry Reding
2012-09-15 20:56 ` Marek Vasut
2012-09-16 2:45 ` Simon Glass
2012-09-16 6:49 ` Thierry Reding
2012-09-17 21:39 ` Simon Glass
2012-09-18 14:54 ` Thierry Reding
2012-09-18 18:24 ` Simon Glass
2012-09-18 18:37 ` Marek Vasut
2012-09-18 19:00 ` Thierry Reding
2012-09-18 19:21 ` Marek Vasut
2012-09-18 19:29 ` Thierry Reding
2012-09-18 19:36 ` Marek Vasut
2012-09-18 20:04 ` Thierry Reding
2012-09-18 20:28 ` Simon Glass
2012-09-18 21:21 ` Marek Vasut
2012-09-18 22:42 ` Simon Glass
2012-09-18 22:44 ` Marek Vasut
2012-09-19 5:45 ` Thierry Reding
2012-09-18 21:20 ` Marek Vasut
2012-09-19 5:46 ` Thierry Reding
2012-09-15 20:19 ` Thierry Reding
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