From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Cache alignment warnings on Tegra (ARM)
Date: Tue, 18 Sep 2012 21:36:18 +0200 [thread overview]
Message-ID: <201209182136.19110.marex@denx.de> (raw)
In-Reply-To: <20120918192916.GA31042@avionic-0098.mockup.avionic-design.de>
Dear Thierry Reding,
[...]
> > Sure, but after you apply the bounce buffer, you can safely invalidate
> > the whole cacheline, so align it up and be done with it.
>
> That's what I proposed to do last time around but it was NAK'ed.
By who?
> At the
> time I didn't ensure that the buffer was actually big enough, which is
> why people didn't like it (data on the stack after the DMA buffer might
> be invalidated as well).
Correct, thus the bounce buffer.
> > > This is by no means Tegra specific. In fact every board that has proper
> > > cache invalidation support should expose this problem.
> >
> > Yea of course, the arm926ejs had this trouble too, see the mxs MMC driver
> > and arm926 cache.c
>
> I suppose we could do something like this as well. If we make sure that
> the buffer is properly aligned and and sized, we could pass the aligned
> end address to invalidate_dcache_range().
>
> Thierry
Best regards,
Marek Vasut
next prev parent reply other threads:[~2012-09-18 19:36 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 16:19 [U-Boot] Cache alignment warnings on Tegra (ARM) Tom Warren
2012-09-12 16:49 ` Stephen Warren
2012-09-12 22:38 ` Marek Vasut
2012-09-12 23:10 ` Stephen Warren
2012-09-12 23:42 ` Marek Vasut
2012-09-14 15:53 ` Simon Glass
2012-09-15 20:01 ` Thierry Reding
2012-09-15 20:11 ` Marek Vasut
2012-09-15 20:41 ` Thierry Reding
2012-09-15 20:56 ` Marek Vasut
2012-09-16 2:45 ` Simon Glass
2012-09-16 6:49 ` Thierry Reding
2012-09-17 21:39 ` Simon Glass
2012-09-18 14:54 ` Thierry Reding
2012-09-18 18:24 ` Simon Glass
2012-09-18 18:37 ` Marek Vasut
2012-09-18 19:00 ` Thierry Reding
2012-09-18 19:21 ` Marek Vasut
2012-09-18 19:29 ` Thierry Reding
2012-09-18 19:36 ` Marek Vasut [this message]
2012-09-18 20:04 ` Thierry Reding
2012-09-18 20:28 ` Simon Glass
2012-09-18 21:21 ` Marek Vasut
2012-09-18 22:42 ` Simon Glass
2012-09-18 22:44 ` Marek Vasut
2012-09-19 5:45 ` Thierry Reding
2012-09-18 21:20 ` Marek Vasut
2012-09-19 5:46 ` Thierry Reding
2012-09-15 20:19 ` Thierry Reding
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