From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Cache alignment warnings on Tegra (ARM)
Date: Wed, 19 Sep 2012 00:44:27 +0200 [thread overview]
Message-ID: <201209190044.27323.marex@denx.de> (raw)
In-Reply-To: <CAPnjgZ3aQ93wmOZTugvPiW=L+YPJi__3y1W7jxZCVtZV3jUyHQ@mail.gmail.com>
Dear Simon Glass,
> Hi,
>
> On Tue, Sep 18, 2012 at 2:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Simon Glass,
> >
> >> Hi,
> >>
> >> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
> >>
> >> <thierry.reding@avionic-design.de> wrote:
> >> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> >> >> Dear Thierry Reding,
> >> >>
> >> >> [...]
> >> >>
> >> >> > > Sure, but after you apply the bounce buffer, you can safely
> >> >> > > invalidate the whole cacheline, so align it up and be done with
> >> >> > > it.
> >> >> >
> >> >> > That's what I proposed to do last time around but it was NAK'ed.
> >> >>
> >> >> By who?
> >> >
> >> > I think it was Simon Glass and Mike Frysinger. They NAK'ed it for very
> >> > valid reason, so I'm not complaining.
> >> >
> >> >> > At the
> >> >> > time I didn't ensure that the buffer was actually big enough, which
> >> >> > is why people didn't like it (data on the stack after the DMA
> >> >> > buffer might be invalidated as well).
> >> >>
> >> >> Correct, thus the bounce buffer.
> >> >
> >> > I don't think we even need the bounce buffer. All that needs to be
> >> > done is guarantee that the buffers passed to the MMC driver are
> >> > properly aligned and sized.
> >> >
> >> > Thierry
> >>
> >> Perhaps a point to make here is that we really don't want every driver
> >> (or even driver stack) implementing bounce buffers to when it is not a
> >> huge effort to change the code that calls them (typically filesystem
> >> code) to do the right thing. The code will be smaller and more
> >> efficient if the alignment issues are dealt with at source IMO.
> >
> > You need the BB for user-case, when user gives you misaligned buffer.
>
> Yes, although I think you are talking about non-filesystem (i.e. raw)
Like fatload ? Fatload doesn't use any interim buffer either, so not only raw.
> access, and it would be odd to read a kernel to a non-cached-aligned
> address. If we want to support that, we can (perhaps even in the
> command itself)., but at least U-Boot's own code should ideally not
> generate unaligned access.
Correct
>
> Regards,
> Simon
>
> > Best regards,
> > Marek Vasut
Best regards,
Marek Vasut
next prev parent reply other threads:[~2012-09-18 22:44 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 16:19 [U-Boot] Cache alignment warnings on Tegra (ARM) Tom Warren
2012-09-12 16:49 ` Stephen Warren
2012-09-12 22:38 ` Marek Vasut
2012-09-12 23:10 ` Stephen Warren
2012-09-12 23:42 ` Marek Vasut
2012-09-14 15:53 ` Simon Glass
2012-09-15 20:01 ` Thierry Reding
2012-09-15 20:11 ` Marek Vasut
2012-09-15 20:41 ` Thierry Reding
2012-09-15 20:56 ` Marek Vasut
2012-09-16 2:45 ` Simon Glass
2012-09-16 6:49 ` Thierry Reding
2012-09-17 21:39 ` Simon Glass
2012-09-18 14:54 ` Thierry Reding
2012-09-18 18:24 ` Simon Glass
2012-09-18 18:37 ` Marek Vasut
2012-09-18 19:00 ` Thierry Reding
2012-09-18 19:21 ` Marek Vasut
2012-09-18 19:29 ` Thierry Reding
2012-09-18 19:36 ` Marek Vasut
2012-09-18 20:04 ` Thierry Reding
2012-09-18 20:28 ` Simon Glass
2012-09-18 21:21 ` Marek Vasut
2012-09-18 22:42 ` Simon Glass
2012-09-18 22:44 ` Marek Vasut [this message]
2012-09-19 5:45 ` Thierry Reding
2012-09-18 21:20 ` Marek Vasut
2012-09-19 5:46 ` Thierry Reding
2012-09-15 20:19 ` Thierry Reding
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